GS8160Z18 ETC, GS8160Z18 Datasheet - Page 4

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GS8160Z18

Manufacturer Part Number
GS8160Z18
Description
18Mb Pipelined and Flow Through Synchronous NBT SRAM
Manufacturer
ETC
Datasheet

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100-Pin TQFP Pin Descriptions
Rev: 2.13a 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DQ
DQ
DQ
DQ
Symbol
A
A
C1
D1
V
A1
B1
ADV
CKE
LBO
2
V
V
A
CK
NC
0
ZZ
–A
B
B
B
B
E
E
E
FT
DDQ
W
G
–DQ
–DQ
–DQ
–DQ
, A
DD
SS
19
C
D
A
B
1
2
3
18
1
A9
B9
C9
D9
Type
I/O
I/O
I/O
I/O
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Byte Write signal for data inputs DQ
Byte Write signal for data inputs DQ
Byte Write signal for data inputs DQ
Byte Write signal for data inputs DQ
4/26
Advance/Load; Burst address counter control pin
Pipeline/Flow Through Mode Control; active low
Burst Address Inputs; Preload the burst counter
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Linear Burst Order; active low
Output driver power supply
Output Enable; active low
Write Enable; active low
Chip Enable; active low
Core power supply
Clock Input Signal
Description
Address Inputs
Address Input
No Connect
GS8160Z18/36T-250/225/200/166/150/133
Ground
C1
D1
A1
B1
-DQ
-DQ
-DQ
-DQ
A9
B9
C9
D9
; active low
; active low
; active low
; active low
© 1998, Giga Semiconductor, Inc.

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