HT82K68 Holtek Semiconductor Inc, HT82K68 Datasheet - Page 15

• Manufacturer Part Number: HT82K68
• Description: Multimedia Keyboard Encoder OTP
• Manufacturer: Holtek Semiconductor Inc

when the reset conditions are met. By examin-
ing the PD and TO flags, the program can dis-
tinguish between different ²chip resets².
Note: ²u² means ²unchanged²
To guarantee that the system oscillator has
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of 1024
system clock pulses when the system powers up
or when it awakes from the HALT state.
TO
u
0
0
1
1
PD
u
u
0
1
1
Reset configuration
RESET reset during power-up
RESET reset during normal
operation
RESET wake-up HALT
WDT time-out during normal
operation
WDT wake-up HALT
Reset circuit
RESET Conditions
Preliminary
15
When a system power-up occurs, the SST delay
is added during the reset period. But when the
reset comes from the RESET pin, the SST delay
is disabled. Any wake-up from HALT will en-
able the SST delay.
The functional unit chip reset status is shown
below.
Timer counter
A timer counter (TMR) is implemented in the
HT82K68E. The timer counter contains an
8-bit programmable count-up counter and the
clock may come from the system clock divided
by 4.
Using the internal instruction clock, there is
only one reference time-base.
There are two registers related to the timer
counter; TMR ([0DH]), TMRC ([0EH]). Two
physical registers are mapped to TMR location;
writing TMR makes the starting value be
placed in the timer counter preload register and
reading TMR gets the contents of the timer
counter. The TMRC is a timer counter control
register, which defines some options.
In the timer mode, once the timer counter
starts counting, it will count from the current
contents in the timer counter to FFH. Once
overflow occurs, the counter is reloaded from
the timer counter preload register and gener-
ates the interrupt request flag (TF; bit 5 of
INTC) at the same time.
PC
Prescaler
WDT
Timer counter
Input/output ports Input mode
SP
000H
Clear
Clear. After master re-
set, WDT begins count-
ing
Off
Points to the top of
the stack
HT82K68E
August 8, 2000