AK5351-VF Asahi Kasei Microsystems, AK5351-VF Datasheet - Page 8

• Manufacturer Part Number: AK5351-VF
• Description: Enhanced Dual bit 20bit ADC
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
0166-E-00
Note 14 : Refer to Serial Data Interface.
Note 15 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK.
Note 16 : The number of LRCK rising edges after PD brought high. The value is in master mode.
Control Clock Frequency
Serial Interface Timing
Power down timing
SWITCHING CHARACTERISTICS
(Ta=25 C; VA,VD,VB=5.0V±10%; C
Master Clock
Serial Data Output Clock
Channel Select Clock(Sampling Frequency)
Slave Mode(SMODE1="L")
Master Mode(SMODE1="H")
PD Pulse width
PD Rising to SDATA Valid
SCLK Period
SCLK Pulse width Low
SCLK Rising to LRCK Edge (Note 15 )
LRCK Edge to SCLK Rising (Note 15 )
LRCK Edge to SDATA MSB Valid
SCLK Falling to SDATA Valid
SCLK Rising to FSYNC Edge(Note 15 )
FSYNC Edge to SCLK Rising(Note 15 )
SCLK Frequency
FSYNC Frequency
SCLK Falling to LRCK Edge
LRCK Edge to FSYNC Rising
SCLK Falling to SDATA Valid
SCLK Falling to FSYNC Edge
Pulse width High
Duty Cycle
Duty Cycle
In slave mode it becomes one LRCK clock(1/fs) longer.
Duty Cycle
384fs:
256fs:
Parameter
Pulse width Low
Pulse width High
Pulse width Low
Pulse width High
(Note 14 )
(Note 16 )
L
=20pF)
- 8 -
f
t
t
f
t
t
f
fs
t
t
t
t
t
t
t
t
t
f
f
t
t
t
t
t
t
CLK
CLKL
CLKH
CLK
CLKL
CLKH
SLK
SLK
SLKL
SLKH
SHLR
LRSH
DLR
DSS
SHF
FSH
SLK
FSYNC
SLR
LRF
DSS
SF
PDW
PDV
Symbol
30.0
30.0
20.0
20.0
144.7
2.048
3.072
-20
-20
25
65
65
30
30
30
30
150
8
min
12.288
18.432
3.072
64fs
50
2fs
50
516
48
1
typ
13.824
20.736
6.912
50
50
20
50
20
54
75
max
[AK5351]
1997/4
MHz
MHz
MHz
Unit
kHz
1/fs
tslk
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%