ILC7082 Impala Linear Corporation, ILC7082 Datasheet - Page 8

• Manufacturer Part Number: ILC7082
• Description: 150MA SOT-23 ULTRA LOW NOISE CMOS RF-LDO REGULATOR
• Manufacturer: Impala Linear Corporation

However, being aware of these current flows, there is also
another potential source of induced voltage noise from the
resistance inherent in the PCB trace. Figure 6 shows where
the additive resistance of the PCB can manifest itself. Again
these resistances may be very small, but a summation of
several currents can develop detectable voltage ripple and
will be amplified by the LDO. Particularly the accumulation
of current flows in the ground plane can develop significant
voltages unless care is taken. With a degree of care, the
ILC7082 will yield outstanding performance.
Printed Circuit Board Layout Guidelines
As was mentioned in the previous section, to take full
advantage of any high performance LDO regulator requires
paying careful attention to grounding and printed circuit
board (PCB) layout.
Figure 7 shows the effects of poor grounding and PCB lay-
out magnified by the ESR and PCB resistances and the
accumulation of current flows.
Note thatparticularly during high output load current, the
LDO regulator’s ground pin and the ground return for C
and C
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current
loop between C
pin will degrade performance of the LDO.
ILC7082 1.3
150mA SOT-23 Ultra Low Noise CMOS RF-LDO™ Regulator
Impala Linear Corporation
NOISE
V
OUT
V
are not at the same potential as the system
I
IN
OUT
C
Figure 6: Inherent PCB resistance
C
IN
OUT
I
OUT
1
, C
R
PCB
NOISE
1
5
R
PCB
and the LDO regulator’s ground
SOT-23-5
ILC7082
2
R
PCB
R
PCB
4
3
ON
OFF
ESR
C
NOISE
[phone]
OUT
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground cur-
rent and noise bypass current return of the LDO regulator.
Note that the key difference here is that C
directly connected to the LDO regulator’s ground pin. The
LDO is then separately connected to the main ground plane
and returned to a single point system ground.
The layout of the LDO and its external components are also
based on some simple rules to minimize EMI and output
voltage ripple.
www.impalalinear.com
Figure 7: Effects of poor circuit layout
April 1999
OUT
and C
NOISE
are
8