MC9S12D64 Motorola, MC9S12D64 Datasheet - Page 71

• Manufacturer Part Number: MC9S12D64
• Description: MC9S12DJ64 Device User Guide V01.17
• Manufacturer: Motorola

Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Vector Address
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
$FFD6, $FFD7
$FFD4, $FFD5
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
$FFCC, $FFCD
Enhanced Capture Timer channel 0
Enhanced Capture Timer channel 1
Enhanced Capture Timer channel 2
Enhanced Capture Timer channel 3
Enhanced Capture Timer channel 4
Enhanced Capture Timer channel 5
Enhanced Capture Timer channel 6
Enhanced Capture Timer channel 7
Enhanced Capture Timer overflow
Unimplemented instruction trap
Pulse accumulator input edge
Pulse accumulator A overflow
Clock Monitor fail reset
Interrupt Source
Real Time Interrupt
COP failure reset
Table 5-1 Interrupt Vector Locations
Port H
Reset
Port J
XIRQ
ATD0
ATD1
SPI0
SCI0
SCI1
SWI
IRQ
Mask
CCR
None
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
(PIEJ7, PIEJ6, PIEJ1, PIEJ0)
MC9S12DJ64 Device User Guide — V01.17
PLLCTL (CME, SCME)
SPICR1 (SPIE, SPTIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
ATDCTL2 (ASCIE)
ATDCTL2 (ASCIE)
IRQCR (IRQEN)
COP rate select
CRGINT (RTIE)
PIEH (PIEH7-0)
Local Enable
PACTL (PAOVI)
TSRC2 (TOI)
PACTL (PAI)
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
SCICR2
SCICR2
None
None
None
None
PIEJ
HPRIO Value
to Elevate
$EE
$EC
$EA
$DE
$DC
$DA
$CE
$CC
$E8
$E6
$E4
$E2
$E0
$D8
$D6
$D4
$D2
$D0
$F2
$F0
–
–
–
–
–
–
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