MC9S12A256 Motorola, MC9S12A256 Datasheet - Page 119
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MC9S12A256
Manufacturer Part Number
MC9S12A256
Description
MC9S12DT256 Device User Guide V03.03
Manufacturer
Motorola
Datasheet
1.MC9S12A256.pdf
(130 pages)
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A.7 SPI
This section provides electrical parametrics and ratings for the SPI.
In Table A-18 the measurement conditions are listed.
A.7.1 Master Mode
In Figure A-5 the timing diagram for master mode with transmission format CPHA=0 is depicted.
In Figure A-6 the timing diagram for master mode with transmission format CPHA=1 is depicted.
Drive mode
Load capacitance C
on all outputs
Thresholds for delay
measurement points
(CPOL 1)
(CPOL 0)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
(INPUT)
MISO
MOSI
SCK
SCK
SS
1
Description
LOAD,
2
5
10
MSB IN
MSB OUT
Figure A-5 SPI Master Timing (CPHA=0)
Table A-18 Measurement Conditions
2
6
4
2
1
4
BIT 6 . . . 1
BIT 6 . . . 1
9
(20% / 80%) VDDX
full drive mode
Value
12
12
50
MC9S12DT256 Device User Guide — V03.03
LSB IN
LSB OUT
13
13
11
Unit
3
pF
—
V
117