P87C51MB2 Philips Semiconductors, P87C51MB2 Datasheet
P87C51MB2
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P87C51MB2 Summary of contents
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... SEE THE LAST 2 PAGES OF THIS DATA SHEET FOR A LIST OF ERRATA RELATED TO THIS PART. P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family with extended memory 64KB/96KB OTP with 2KB/3KB RAM Preliminary specification hilips Semiconductors INTEGRATED CIRCUITS 2001 Apr 06 ...
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... The P87C51Mx2 represents the first microcontroller based on Philips Semiconductors’ new 51MX core. The P87C51MC2 features 96 Kbytes of OTP program memory and 3 Kbytes of data SRAM, while the P87C51MB2 has 64 Kbytes of OTP and 2 Kbytes of RAM. In addition, both devices are equipped with a Programmable Counter Array (PCA), a watchdog timer that can be configured to different time ranges through SFR bits, as well as two enhanced UARTs or one enhanced UART and an SPI. Philips Semiconductors’ ...
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... PART ORDER NUMBER 1 P87C51MB2BA 2 P87C51MC2BA 2001 Apr 06 MEMORY TEMPERATURE RANGE AND OTP RAM PACKAGE 64 KB 2048 +70°C, PLCC44 2.7-5. 3072 +70°C, PLCC44 2.7-5.5V 3 Preliminary specification P87C51MB2/P87C51MC2 FREQUENCY V VOLTAGE RANGE DD DD 2.7-5.5V 4.5-5.5V 4.5-5.5V 0-12MHz 0-24MHz SOT187-2 4.5-5.5V 0-12MHz 0-24MHz SOT187-2 DWG # ...
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... OTP with 2KB/3KB RAM LOGIC SYMBOL RXD0 TXD0 INT0 INT1 MISO RXD1 SS TXD1 2001 Apr P87C51Mx2 RST EA/Vpp PSEN ALE/PROG 4 Preliminary specification P87C51MB2/P87C51MC2 T2 T2EX ECI CEX0 CEX1 MOSI CEX2 SPICLK CEX3 CEX4 XTAL2 XTAL1 ...
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... P3.1/TXD0 35 14 P3.2/INT0 36 15 P3.3/INT1 37 16 P3.4/ P3.5/ P3.6/ P3.7/ XTAL2 42 21 XTAL1 Preliminary specification P87C51MB2/P87C51MC2 1 (NC P2.0/A8/A16 P2.1/A9/A17 P2.2/A10/A18 P2.3/A11/A19 P2.4/A12/A20 P2.5/A13/A21 P2.6/A14/A22 P2.7/A15 PSEN ALE 1 P4.1/TXD1/SS EA/Vpp P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 V DD ...
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... Configurable I/Os Configurable I/Os Configurable I/Os Crystal or Resonator 2001 Apr 06 High Performance 80C51 CPU (51MX Core) Internal Bus Data RAM Port 4 Port 3 Port 2 Port 1 Port 0 Oscillator 6 Preliminary specification P87C51MB2/P87C51MC2 UART 0 Baud Rate Generator UART 1 SPI Timer0 Timer1 Watchdog Timer PCA (Programmable Counter Array) Timer2 ...
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... Capture/Compare External I/O for PCA module 4 P3.0 RXD0 Serial input port 0 P3.1 TXD0 Serial output port 0 P3.2 INT0 External interrupt 0 P3.3 INT1 External interrupt 1 P3.4 T0 Timer0 external input P3.5 T1 Timer1 external input P3.6 WR External data memory write strobe P3.7 RD External data memory read strobe 7 Preliminary specification P87C51MB2/P87C51MC2 ). Port 2 emits the high-order IL ...
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... Connecting the second pair pins is not required. However, they may be connected in addition to the primary V DD pins to improve power distribution, reduce noise in output signals, and improve DD 8 Preliminary specification P87C51MB2/P87C51MC2 permits a power-on reset using only an external SS and and SS ...
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... FCH FDH FEH EAH EBH ECH EDH EEH DAH - ECOM_0 CAPP_0 DBH - ECOM_1 CAPP_1 DCH - ECOM_2 CAPP_2 DDH - ECOM_3 CAPP_3 DEH - ECOM_4 CAPP_4 9 Preliminary specification P87C51MB2/P87C51MC2 EXTRAM LPEP GF2 BRATE8 BRATE7 BRATE6 BRATE5 BRATE4 BRATE0 - - - - - - S0BRGS CAPN_0 ...
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... F8H - - - F7H - - - ‡ FFH 80H AD7 AD6 AD5 CEX2/ 90H CEX4 CEX3 SPICLK 10 Preliminary specification P87C51MB2/P87C51MC2 CCF4 CCF3 CCF2 CCF1 - - CPS1 CPS0 ES0/ ET1 EX1 ET0 ES0R ESPI ES1T ES0T ...
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... DBMOD_ ‡ 84H INTLO_1 CIDIS_1 1 81H E2H SSIG SPEN DORD E1H SPIF SPWCOL - E3H ‡ FBH 11 Preliminary specification P87C51MB2/P87C51MC2 AD11/ AD10/ AD9/ AD12/AD20 AD19 AD18 AD17 INT1 INT0 TxD0 ‡ ‡ ‡ ‡ ...
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... TF0 88H TF2 EXF2 RCLK C8H - - - C9H 8CH 8DH CDH 8AH 8BH CCH 89H GATE C/T M1 A6H ‡ 8FH - - - 12 Preliminary specification P87C51MB2/P87C51MC2 TR0 IE1 IT1 IE0 TCLK EXEN2 TR2 C/T2 CP/RL2 - - - T2OE DCEN M0 GATE C WDPRE2 WDPRE1 WDPRE0 Reset ...
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... EI10 (IEN1.1) 0043h EI11 (IEN1.2) 004Bh EI11 (IEN1.3) 005Bh EI12 (IEN1.4) 0063h EI13 (IEN1.5) 006Bh EI13 (IEN1.6) 0073h EI14 (IEN1.7) 13 Preliminary specification P87C51MB2/P87C51MC2 Interrupt Polling Power Down Priority Priority Wakeup IP0H.0, IP0.0 1 (highest) IP0H.1, IP0.1 2 IP0H.2, IP0.2 3 IP0H.3, IP0.3 4 IP0H.4, IP0.4 6 IP0H ...
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... Philips Semiconductors 80C51 8-bit microcontroller family with extended memory 64KB/96KB OTP with 2KB/3KB RAM DATA RAM The P87C51MB2 and P87C51MC2 have 2 Kbytes and 3 K bytes of on-chip RAM respectively. Usages of the different data segments are described in the 51MX Architecture Reference. Type DATA ...
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... When 1, bit 7 of S0CON and S1CON will be used for framing error status for UART 0 and 1 respectively. PCON.6 also determines when the UART receive interrupts RI_0 and RI_1 occur in UART modes (Refer to User Manual for details.) 2001 Apr 06 P87C51MB2/P87C51MC2 51MX Extended SFR SFR Location Location ...
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... Baud Rate for UART OSC * f /(BRATE 16+16) OSC * f /(BRATE 16+16) OSC * f /(BRATE 16+16) OSC 16 Preliminary specification P87C51MB2/P87C51MC2 Receive/Transmit Baud Rate for UART OSC * T1_rate/32 * T1_rate/16 * T2_rate/ /(BRATE 16+16) OSC f /32 OSC f /16 OSC * T1_rate/32 * T1_rate/16 * T2_rate/ /(BRATE 16+16) ...
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... No program security features enabled. EEPROM is programmable and verifiable. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory sampled and latched on Reset, and further programming of the EPROM is disabled. Same as 2, also verification is disabled. Same as 3, external execution is disabled. 17 Preliminary specification P87C51MB2/P87C51MC2 ...
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... Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted. 2001 Apr 06 PARAMETER pin per I/O pin OL 18 Preliminary specification P87C51MB2/P87C51MC2 RATING UNIT -55 to +125 °C -65 to +150 ° 13 +0. ...
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... ALE and PSEN to momentarily fall below the approximately 2 V for 4.5V < test conditions the oscillator frequency in MHz. OSC 19 Preliminary specification P87C51MB2/P87C51MC2 LIMITS 1 MIN TYP MAX 0.2V -0.5 DD 0.2V +0 0. 0 -75 -650 ± ...
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... ALE is tested except when ALE is off then V OH1 10. Pin capacitance is characterized but not tested. 2001 Apr 06 must be externally limited as follows may exceed the related specification. Pins are not guaranteed to sink current OL is the voltage specification Preliminary specification P87C51MB2/P87C51MC2 ...
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... CLCX - CHCX CHCX CLCL CLCX CLCL CHCX Preliminary specification P87C51MB2/P87C51MC2 4.5V < VDD < 5. =24MHz Variable Clock UNIT OSC MIN MAX MIN MAX 0 24 MHz 41.5 t -33 8 CLCL t -12 4 CHCX t -12 4 CLCX 2t -54 ...
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... TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD - - 0 0 TBD TBD TBD TBD TBD TBD TBD TBD 22 Preliminary specification P87C51MB2/P87C51MC2 4.5V < VDD < 5. =24MHz Variable Clock UNIT OSC MIN MAX MIN MAX 6t 250 ns CLCL -110 98 ns CLCL t - ...
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... AVLL t - Time for ALE low to PSEN low LLPL t LHLL ALE t LLPL PSEN t AVLL t LLAX PORT 0 A0-A7 PORT 2 Figure 1: External Program Memory Read Cycle (Non-Extended Memory Cycle) 2001 Apr 06 t PLPH t LLIV t PLIV t PLAZ t PXIX INSTR IN t AVIV P2.0-P2.7 OR A8-A15 23 Preliminary specification P87C51MB2/P87C51MC2 t PXIZ A0-A7 ...
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... Figure 3: External Data Memory Read Cycle (Non-Extended Memory Cycle) 2001 Apr 06 t PLPH t LLIV t PLIV t PLAZ INSTR IN t AVIV1 A8-A15 t LLDV t t LLWL RLRH t t RLAZ RLDV t RHDX DATA in t AVDV P2.0-P2.7 OR A8-A15 24 Preliminary specification P87C51MB2/P87C51MC2 t PXIZ t PXIX A0-A7 t WHLH t RHDZ A0-A7 FROM PCL INSTR IN ...
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... Figure 5: External Data Memory Write Cycle (Non-Extended Memory Cycle) 2001 Apr 06 t LLDV t t LLWL RLRH t t RLAZ RLDV t RHDX DATA in t AVWL1 t AVDV1 A8-A15 t t LLWL WLWH t QVWX t QVWH DATA OUT t AVWL P2.0-P2.7 OR A8-A15 25 Preliminary specification P87C51MB2/P87C51MC2 t WHLH t RHDZ A0-A7 FROM PCL INSTR IN t WHLH t WHQX A0-A7 FROM PCL INSTR IN ...
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... LLWL WLWH t QVWX t QVWH DATA OUT t AVWL1 A8-A15 XLXL t XHQX XHDX VALID VALID VALID Figure 7: Shift Register Mode Timing 26 Preliminary specification P87C51MB2/P87C51MC2 t WHLH t WHQX A0-A7 FROM PCL VALID VALID VALID INSTR IN 7 SET TI VALID SET RI ...
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... SPICLKL SPIR t SPICLKH t t SPIF SPICLKL t SPICLKH t SPIDH MSB/LSB in t SPIOH Master MSB/LSB out Figure 9: SPI Master Timing (CPHA = 1) 27 Preliminary specification P87C51MB2/P87C51MC2 t SPIR LSB/MSB in t SPIDV Master LSB/MSB out t SPIR LSB/MSB in t SPIDV Master LSB/MSB out t SPIR t SPIDV t SPIR ...
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... SPIR t SPICLKH t t SPIOH SPIOH t t SPIDV SPIDV Slave MSB/LSB out t t SPIDSU SPIDH MSB/LSB in Figure 11: SPI Slave Timing (CPHA = 1) 28 Preliminary specification P87C51MB2/P87C51MC2 t SPILAG t t SPIOH SPIOH t SPIDV Slave LSB/MSB out Not defined t t SPIDSU SPIDH LSB/MSB in t SPILAG t SPIOH ...
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... CLOCK SIGNAL Figure 13 2001 Apr 06 V -0.5V DD 0.7V DD 0.45V 0.2V -0. CLCX CHCL t CLCL Figure 12: External Clock Drive V DD RST (NC) XTAL2 XTAL1 V SS Test Condition, Active Mode (All other pins are disconnected) 29 Preliminary specification P87C51MB2/P87C51MC2 t CHCX t CLCH ...
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... Figure 15: Clock Signal Waveform for I 2001 Apr 06 RST (NC) XTAL2 XTAL1 V SS Test Condition, Idle Mode (All other pins are disconnected) V -0.5V DD 0.7V DD 0.45V 0.2V -0. CLCX CHCL t CLCL Tests in Active and Idle Modes Preliminary specification P87C51MB2/P87C51MC2 CHCX t CLCH = t = 5ns CLCH CHCL ...
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... Philips Semiconductors 80C51 8-bit microcontroller family with extended memory 64KB/96KB OTP with 2KB/3KB RAM Figure 16: I Test Condition, Power Down Mode (All other pins are disconnected 2001 Apr 06 RST (NC) XTAL2 XTAL1 Preliminary specification P87C51MB2/P87C51MC2 2.0V to 5.5V) DD ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors yyyy mmm dd [1] Copyright Philips Electronics North America Corporation 2001 Document order number: 4 Preliminary specification P87C51MB2/P87C51MC2 All rights reserved. Printed in U.S.A. Date of release: 04-01 9397 750 08199 ...
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... The UART double buffering will be implemented on the next release. Work-around: None. Deviation #6 SPI block will be implemented on the next release. Work-around: None. Deviation #7 Security bits are not 100% compatible with past 80c51 products. Work-around: The security bits will be compatible on the next release. 2001 Apr 06 P87C51MB2/P87C51MC2 1 Errata Version 1.0 ...
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... This requires an increased data hold time. This will be fixed on the next release. Deviation #9 The PCA Watchdog timer function may not function properly at 24 MHz f selection is set to “internal clock, f Work-around: None. This will be fixed on the next release. 2001 Apr 06 /2”. OSC 2 Errata P87C51MB2/P87C51MC2 when the PCA Count Pulse OSC ...