P89LPC924 Philips Semiconductors, P89LPC924 Datasheet
P89LPC924
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P89LPC924 Summary of contents
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... The P89LPC924/925 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC924/925 in order to reduce component count, board space, and system cost. 2. Features 2 ...
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... Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. Only power and ground connections are required to operate the P89LPC924/925 when internal reset option is selected. Four interrupt priority levels. Eight keypad interrupt inputs, plus two additional external interrupt inputs. ...
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... Part options Flash memory Temperature range + +85 C Rev. 03 — 15 December 2004 P89LPC924/925 Version SOT360-1 SOT360-1 Frequency 0 MHz to 18 MHz 0 MHz to 18 MHz © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... INTERNAL BUS 256-BYTE DATA RAM PORT 3 PORT 1 PORT 0 KEYPAD INTERRUPT CPU CLOCK ON-CHIP CONFIGURABLE RC OSCILLATOR OSCILLATOR Rev. 03 — 15 December 2004 P89LPC924/925 UART REAL-TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 WATCHDOG TIMER AND OSCILLATOR ANALOG COMPARATORS ADC1/DAC1 POWER MONITOR (POWER-ON RESET, BROWNOUT RESET) 002aaa786 © ...
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... P1 RST/P1 XTAL1/P3 CLKOUT/XTAL2/P3 INT1/P1 SDA/INT0/P1 SCL/T0/P1 002aaa787 Rev. 03 — 15 December 2004 P89LPC924/925 P0.1/CIN2B/KBI1/AD10 P0.2/CIN2A/KBI2/AD11 P0.3/CIN1B/KBI3/AD12 P0.4/CIN1A/KBI4/AD13/DAC1 P0.5/CMPREF/KBI5 V DD P0.6/CMP1/KBI6 P0.7/T1/KBI7 P1.0/TXD P1.1/RXD © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... T1 — Timer/counter 1 external count input or overflow output. I KBI7 — Keyboard input 7. 9397 750 14471 Product data 8-bit microcontrollers with accelerated two-clock 80C51 core and Table 8 “DC electrical characteristics” Rev. 03 — 15 December 2004 P89LPC924/925 Section 8.13.1 “Port for details. © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Table 8 “DC electrical characteristics” serial clock input/output serial data input/output. Rev. 03 — 15 December 2004 P89LPC924/925 Section 8.13.1 “Port configurations” for details. P1.2 - P1.3 are open drain when DD will fall below the DD falls below the minimum specified DD © ...
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... CIN2B KBI2 CIN2A KBI3 CIN1B KBI4 CIN1A KBI5 CMPREF KBI6 CMP1 KBI7 T1 XTAL2 XTAL1 Rev. 03 — 15 December 2004 P89LPC924/925 Section 8.13.1 “Port for details TxD RxD T0 SCL INT0 SDA INT1 RST 002aaa789 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Product data 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 03 — 15 December 2004 P89LPC924/925 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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Table 4: Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H ADCON1 A/D control register 1 97H ADINS A/D input select A3H ...
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Table 4: Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. FMCON Program Flash control (Read) E4H Program Flash control (Write) E4H FMDATA Program Flash data ...
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Table 4: Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. P0* Port 0 80H Bit address P1* Port 1 90H Bit address P3* Port 3 ...
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... BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC924/925 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000. ...
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... Remark: Please refer to the P89LPC924/925 User’s Manual for a more detailed functional description. 8.1 Enhanced CPU The P89LPC924/925 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. ...
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... Idle mode, it may be turned off prior to entering Idle, saving additional power. 8.3 On-chip RC oscillator option The P89LPC924/925 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz room temperature ...
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... Low freq. OSCCLK RC OSCILLATOR (7.3728 MHz) WATCHDOG OSCILLATOR (400 kHz) PCLK TIMER 0 and BAUD RATE TIMER 1 GENERATOR Rev. 03 — 15 December 2004 P89LPC924/925 RTC ADC1/ DAC1 CCLK DIVM CPU 2 WDT UART 002aaa790 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Philips Semiconductors 8.6 CPU Clock (CCLK) wake-up delay The P89LPC924/925 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus 60 to 100 s ...
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... Philips Semiconductors 8.9 A/D converter 8.9.1 General description The P89LPC924/925 has an 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter module. A block diagram of the A/D converter is shown in Figure circuit providing an input signal to one of two comparator inputs. The control logic in combination with the successive approximation register (SAR) drives a digital-to-analog converter which provides the other input to the comparator ...
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... ADC clock of 3.3 MHz A single input channel can be selected for A single input channel can be Any combination of the four input channels Any combination of the four input Rev. 03 — 15 December 2004 P89LPC924/925 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... This special mode allows ‘single-stepping’ auto scan An A/D conversion is started by the overflow of Timer 0. Once Programming this mode immediately starts a conversion. This An A/D conversion is started by rising or falling edge of P1.4. Once Rev. 03 — 15 December 2004 P89LPC924/925 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... CODE Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC924/925 has 4 kB on-chip Code memory. 9397 750 14471 Product data 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 03 — ...
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... In edge-triggered mode if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request external interrupt is enabled when the P89LPC924/925 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to ...
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... Fig 6. Interrupt sources, interrupt enables, and power-down wake-up sources. 8.13 I/O ports The P89LPC924/925 has three I/O ports: Port 0, Port 1, and Port 3. Ports 0 and 1 are 8-bit ports, and Port 2-bit port. The exact number of I/O pins available depend upon the clock and reset options chosen, as shown in ...
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... Philips Semiconductors 8.13.1 Port configurations All but three I/O port pins on the P89LPC924/925 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. ...
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... Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only or open-drain. Every output on the P89LPC924/925 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to specifi ...
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... Idle mode. 8.15.2 Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC924/925 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage V was entered. SFR contents are not guaranteed after V therefore it is highly recommended to wake up the processor via reset in this case ...
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... For any other reset, previously set flag bits that have not been cleared will remain set. 8.16.1 Reset vector Following reset, the P89LPC924/925 will fetch instructions from either address 0000h or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address = 00h. ...
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... Real-Time clock/system timer The P89LPC924/925 has a simple Real-Time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. The Real-Time clock can be a wake- interrupt source. The Real-Time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all ‘ ...
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... Baud Rate Generator (described in selection”). 8.19.5 Baud rate generator and selection The P89LPC924/925 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate ...
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... If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. 9397 750 14471 Product data 8-bit microcontrollers with accelerated two-clock 80C51 core bit (bit 8) in double buffering (Modes 1, 2 and 3) Rev. 03 — 15 December 2004 P89LPC924/925 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... I C-BUS P1.3/SDA P1.2/SCL OTHER DEVICE WITH I P89LPC920/921/922 INTERFACE 2 C-bus configuration. Rev. 03 — 15 December 2004 P89LPC924/925 Figure 8. The P89LPC924/925 device R P SDA SCL OTHER DEVICE 2 2 C-BUS WITH I C-BUS INTERFACE 002aaa420 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... SERIAL CLOCK OUTPUT GENERATOR STAGE TIMER 1 OVERFLOW P1.2 I2CON I2SCLH SCL DUTY CYCLE REGISTERS I2SCLL STATUS BUS I2STAT 2 C-bus serial interface block diagram. Rev. 03 — 15 December 2004 P89LPC924/925 8 I2ADR COMPARATOR SHIFT REGISTER ACK I2DAT 8 CCLK TIMING & CONTROL LOGIC INTERRUPT CONTROL REGISTERS & 8 ...
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... Philips Semiconductors 8.21 Analog comparators Two analog comparators are provided on the P89LPC924/925. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be confi ...
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... In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs. 9397 750 14471 Product data 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 03 — 15 December 2004 P89LPC924/925 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few few seconds. Please refer to the P89LPC924/925 User’s Manual for more details. MOV WFEED1, #0A5H ...
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... Philips Semiconductors 8.25 Flash program memory 8.25.1 General description The P89LPC924/925 Flash memory provides in-circuit electrical erasure and programming. The Flash can be read, erased, or written as bytes. The Sector and Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. In-System Programming and standard parallel programming are both available ...
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... Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector from 1C00H to 1FFFH in the P89LPC925 or the 1 kB sector from 0C00H to 0FFFH in the P89LPC924. Instead, the page erase function can be used to erase the eight 64-byte pages which comprise the lower 512 bytes of the sector ...
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... Flash sectors, pages, security bits, configuration bytes, and device identification. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FF03H. Please see the P89LPC924/925 User’s Manual for additional details. In-Circuit Programming (ICP): allow commercial programmers to program and erase these devices without removing the microcontroller from the system ...
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... Conditions SS SS based on package heat transfer, not device power consumption Table 7 may cause permanent damage to the device. This is a stress rating only and functional of this specification are not implied. Rev. 03 — 15 December 2004 P89LPC924/925 Min Max 55 +125 65 +150 - V + 0.5 DD ...
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... push-pull mode quasi-bidirectional mode [ [7 Rev. 03 — 15 December 2004 P89LPC924/925 [1] Typ Max Unit ...
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... Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest when V is approximately 9397 750 14471 Product data 8-bit microcontrollers with accelerated two-clock 80C51 core …continued Conditions 2.4 V < V < 3 for steady state (non-transient) limits Rev. 03 — 15 December 2004 P89LPC924/925 [1] Min Typ Max Unit 2.40 - 2.70 V 1.11 1.23 1. ...
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... Figure CLCL see Figure CLCL see Figure see Figure CLCL CLCL - t CLCL - 0 150 - Rev. 03 — 15 December 2004 P89LPC924/925 MHz Unit osc Min Max 7.189 7.557 MHz 320 520 kHz - - MHz - - MHz - 50 ns 125 - ...
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... CLCL 13 t CLCL - - 150 has reached its specified level. When system power is removed V DD falls below the minimum specified operating voltage. DD Rev. 03 — 15 December 2004 P89LPC924/925 MHz Unit osc Max Min Max 7.557 7.189 7.557 MHz 520 ...
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... XHDX Valid Valid Valid Valid 0 0 CHCL t CLCX t C Conditions Min Rev. 03 — 15 December 2004 P89LPC924/925 Set TI Valid Valid Valid Set RI 002aaa425 t CHCX t CLCH 002aaa416 Typ Max Unit - - - 002aaa426 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Product data 8-bit microcontrollers with accelerated two-clock 80C51 core Conditions Min - 0 [ < V < Conditions Min 100 kHz - - A/D enabled - Rev. 03 — 15 December 2004 P89LPC924/925 Typ Max Unit - 0 250 500 Typ Max Unit 0 0 ...
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... 2 scale (1) ( 0.2 6.6 4.5 6.6 0.65 1 0.1 6.4 4.3 6.2 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 15 December 2004 P89LPC924/925 SOT360 detail X ( 0.75 0.4 0.5 8 0.2 0.13 0.1 0.50 0.3 0.2 0 EUROPEAN ISSUE DATE PROJECTION 99-12-27 03-02-19 © ...
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... Added 18 MHz information. 02 20040615 - Product data (9397 750 13459) 01 20040309 - Objective data (9397 750 12879) 9397 750 14471 Product data 8-bit microcontrollers with accelerated two-clock 80C51 core Rev. 03 — 15 December 2004 P89LPC924/925 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Licenses Purchase of Philips I Rev. 03 — 15 December 2004 P89LPC924/925 2 C components 2 Purchase of Philips I C components conveys a license 2 under the Philips’ ...
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... Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.24.1 Software reset 8.24.2 Dual data pointers 8.25 Flash program memory 8.25.1 General description 8.25.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.25.3 ISP and IAP capabilities of the P89LPC924/925 . . . 36 8.26 User configuration bytes . . . . . . . . . . . . . . . . . . . . . . 38 8.27 User sector security bytes . . . . . . . . . . . . . . . . . . . . 38 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 42 12 Comparator electrical characteristics . . . . . . . . . . . 45 13 A/D converter electrical characteristics ...