T89C51CC01 Atmel, T89C51CC01 Datasheet - Page 135

• Manufacturer Part Number: T89C51CC01
• Description: Enhanced 8-Bit Microcontroller
• Manufacturer: Atmel

ADC Converter
Operation
Voltage Conversion
Clock Selection
4129K–CAN–01/05
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
After completion of the A/D conversion, the ADSST bit is cleared by hardware.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is
available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is
set, an interrupt occur when flag ADEOC is set (see Figure 62). Clear this flag for re-
arming the interrupt.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
Note:
Table 107. Selected Analog input
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note:
The ADC clock is the same as CPU.
The maximum clock frequency is defined in the DC parmeters for A/D converter. A pres-
caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.
f
with
if PRS > 0 then f
if PRS = 0 then f
ADC
= fcpu clock/ (4 (or 2 in X2 mode)* PRS )
1. Always leave Tsetup time before starting a conversion unless ADEN is permanently
ADCIN should not exceed VAREF absolute maximum range (see “Absolute Maximum
Ratings” on page 148)
SCH2
(1)
0
0
0
0
1
1
1
1
high. In this case one should wait Tsetup only before the first conversion.
ADC
ADC
= F
= F
periph
periph
/ 2 x PRS
/ 64
SCH1
0
0
1
1
0
0
1
1
SCH0
0
1
0
1
0
1
0
1
T89C51CC01
Selected Analog input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
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