HIP6503CB Intersil Corporation, HIP6503CB Datasheet

HIP6503CB

Manufacturer Part Number

HIP6503CB

Description

Multiple Linear Power Controller with ACPI Control Interface

Manufacturer

Intersil Corporation

Datasheet

1.HIP6503CB.pdf (14 pages)

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Multiple Linear Power Controller with

ACPI Control Interface

The HIP6503 complements either an HIP6020 or an

HIP6021 in ACPI-compliant designs for microprocessor and

computer applications. The IC integrates four linear

controllers/regulators, switching, monitoring and control

functions into a 20 pin SOIC package. One linear controller

generates the 3.3V

supply’s 5VSB output, powering the south bridge and the

PCI slots through an external pass transistor during sleep

states (S3, S4/S5). A second transistor is used to switch in

the ATX 3.3V output for operation during S0 and S1/S2

(active) operating states. A linear controllers/regulator

supplies at choice either of 2.5V or 3.3V memory power

through external pass transistors (switch for 3.3V setting) in

active states. During sleep states, integrated pass

transistors supply the sleep power. Another controller

powers up the 5V

output in active states, and the ATX 5VSB in sleep states.

Two internal regulators output both a dedicated, noise-free

2.5V clock chip supply, as well as a 1.8V ICH2 resume well

voltage. The HIP6503’s operating mode (active outputs or

sleep outputs) is selectable through two digital control pins,

S3 and S5. Enabling sleep state support on the 5V

output is offered through the EN5VDL pin. In active state, the

3.3V

use external N-channel pass MOSFETs to connect the

outputs directly to the 3.3V input supplied by an ATX power

supply, for minimal losses. In sleep state, power delivery on

both outputs is transferred to NPN transistors - external to

the controller on the 3.3V

2.5V

output is performed through an external NPN transistor. The

transistors. In sleep states, a PMOS (or PNP) transistor

conducts the current from the ATX 5VSB output; while in

active state, current ﬂow is transferred to an NMOS

transistor connected to the ATX 5V output. The operation of

the 5V

S3 and S5 pins, but that of the EN5VDL pin as well. The

3.3V

as the ATX 5VSB voltage is applied to the chip. The 2.5V

output is only active during S0 and S1/S2, and uses the 3V3

pin as input source for its internal pass element.

Ordering Information

HIP6503CB

HIP6503EVAL1

PART NUMBER

DUAL

MEM

DUAL

output is powered through two external MOS

/3.3V

output is dictated not only by the status of the

MEM

DUAL

and 2.5V

and 1.8V

DUAL

. Active state regulation on the 2.5V

Evaluation Board

RANGE (

TEMP.

0 to 70

plane by switching in the ATX 5V

/3.3V

DUAL

MEM

/3.3V

outputs are active for as long

/3.3V

voltage plane from the ATX

20 Ld SOIC

1-888-INTERSIL or 321-724-7143

Data Sheet

PACKAGE

MEM

, internal on the

linear regulators

DUAL

M20.3

PKG.

NO.

MEM

CLK

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil and Design is a trademark of Intersil Corporation.

Features

• Provides 5 ACPI-Controlled Voltages

• Excellent Output Voltage Regulation

• Small Size

• Dual Memory Voltage Selection Via FAULT/MSEL Pin

• Undervoltage Monitoring of All Outputs with Centralized

Applications

• Motherboard Power Regulation for ACPI-Compliant

Pinout

- 5V

- 3.3V

- 2.5V

- 1.8V

- 3.3V

- 2.5V

- 1.8V

- Very Low External Component Count

- 2.5V for RDRAM Memory

- 3.3V for SDRAM Memory

FAULT Reporting and Temperature Shutdown

Computers

Sleep State Only

Both Operational States (3.3V

DUAL

MEM

CLK

DUAL

MEM

, 2.5V

3V3DLSB

ICH2 Resume

EN5VDL

June 2000

USB/Keyboard/Mouse (Active/Sleep)

Clock/Processor Terminations (Active Only)

/3.3V

1V8SB

3V3DL

/3.3V

RDRAM or 3.3V

/3.3V

1V8IN

5VSB

VCLK

3V3

CLK

MEM

Outputs: 2.0% Over Temperature

PCI/Auxiliary/LAN (Active/Sleep)

Output: 2.0% Over Temperature;

TOP VIEW

HIP6503

(SOIC)

MEM

File Number

MEM

SDRAM (Active/Sleep)

VSEN2

5VDL

5VDLSB

DLA

FAULT/MSEL

in sleep only)

DRV2

12V

GND

HIP6503

Intersil Corporation 2000

4882.1

Related parts for HIP6503CB

HIP6503CB Summary of contents

Page 1

... ATX 5VSB voltage is applied to the chip. The 2.5V output is only active during S0 and S1/S2, and uses the 3V3 pin as input source for its internal pass element. Ordering Information TEMP. o PART NUMBER RANGE ( C) PACKAGE HIP6503CB SOIC HIP6503EVAL1 Evaluation Board 1 1-888-INTERSIL or 321-724-7143 Features • Provides 5 ACPI-Controlled Voltages - ...

Page 2

Block Diagram 12V 12V MONITOR 10.8V/9.8V 1V8IN EA3 + - TO UV DETECTOR 1V8SB TO 5VSB 40 A FAULT/MSEL UV DETECTOR UV COMP 4.15V 5VDL GND 3V3DL 5V 3V3 3V3DLSB EA4 - + 4.4V/3.4V 3V3 MONITOR 5V MONITOR 2.97V/2.8V 4.5V/4.25V ...

Page 3

Simpliﬁed Power System Diagram +5V IN +12V IN +5V SB +3.3V IN 1. 3.3V /3.3V DUAL SB 3.3V FAULT\MSEL SHUTDOWN SX 2 EN5VDL Typical Application +5V IN +12V IN +5V SB +3. OUT1 1.8V ...

Page 4

Absolute Maximum Ratings Supply Voltage +7.0V 5VSB 12V. . ...

Page 5

Electrical Speciﬁcations Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued) PARAMETER (Note 2) DRV2 Output Drive Current DRV2 Output Impedance 3.3V /3.3V LINEAR REGULATOR (V DUAL SB Sleep State Regulation 3V3DL Nominal Voltage Level ...

Page 6

Functional Pin Description 3V3 (Pin 7) Connect this pin to the ATX 3.3V output. This pin provides the output current for the 2V5CLK pin, and is monitored for power quality. 5VSB (Pin 2) Provide a very well de-coupled 5V bias ...

Page 7

This pin is the output of the internal 1.8V regulator (V This internal regulator operates for as long as 5VSB is applied to the HIP6503. This pin is monitored for under- voltage events. 1V8IN (Pin 20) This ...

Page 8

S3 S5 3.3V, 5V, 12V 3V3DLSB DLA 3V3DL 5VDLSB 5VDL FIGURE 5. 5V TIMING DIAGRAM FOR EN5VDL = 0; DUAL 3V /3V DUAL SB Not shown in these diagrams is the deglitching feature used to protect against false sleep ...

Page 9

ATX outputs are well within regulation limits. SOFT-START INTO ACTIVE STATES (S0, S1) If both S3 and S5 are logic high at the time the 5VSB is applied, the HIP6503 will assume active state wake-up ...

Page 10

In HIP6503 applications, loss of any one active ATX output (3. 12V ; as detected by the on-board voltage monitors) during active state operation causes the chip to switch to S5 sleep state, ...

Page 11

high-frequency decoupling capacitors should be placed as close as possible to the load they are decoupling; the ones decoupling the controller close to the controller pins, the ones decoupling the load close to the load connector or the load itself ...

Page 12

CAPACITANCE ( F) FIGURE 11. C OUTPUT CAPACITOR OUT4 Input Capacitors Selection The input capacitors for an HIP6503 application have to have a sufﬁciently low ESR as to not allow the input voltage to ...

Page 13

... ATX supply outputs. Q4 can also be a PNP, such as an MMBT2907AL. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN9901. ), the ICH2 Also see Intersil Corporation’s web page OUT3 (www.intersil.com) or Intersil’s AnswerFAX MEM clock voltage (321-724-7800) for the latest information ...

Page 14

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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