W25P240A-6A Winbond, W25P240A-6A Datasheet - Page 10

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W25P240A-6A

Manufacturer Part Number
W25P240A-6A
Description
64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
Manufacturer
Winbond
Datasheet
Timing Waveforms, continued
Write Cycle Timing
Data-Out
BW[8:1]
Data-In
A[15:0]
ADSC
ADSP
BWE
ADV
CLK
CE
GW
OE
T
High-Z
High-Z
ADSS
T
Single Write
CES
T
AS
WR1
T
T
T
T
AH
DON'T CARE
UNDEFINED
ADVS
ADCS
CEH
T
T
T
T
ADSH
WS
WS
WS
T
DS
WR1
1a
ADV must be inactive for ADSP write
T
DH
T
T
T
T
T
ADCH
ADVH
WH
WH
WH
WR2
T
KH
T
T
CYC
KL
GW allows processor address (and BE = BWE)
WR2
BW[8:1] are applied only to first cycle of WR2
2a
Burst Write
to be pipelined during a writeback
- 10 -
2b
ADSP is blocked by CE inactive
CE masks ADSP
2c
2d
Write
ADSC initiated write
WR3
WR3
3a
Unselected with CE
Unselected
W25P240A

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