M5M51008CFP Mitsubishi, M5M51008CFP Datasheet - Page 2

• Manufacturer Part Number: M5M51008CFP
• Description: 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
• Manufacturer: Mitsubishi

FUNCTION
The operation mode of the M5M51008C series are determined by
a combination of the device control inputs S
the low level S
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S
whichever occurs first,requiring the set-up and hold time relative to
these edge to be maintained. The output enable input OE directly
controls the output stage. Setting the OE at a high level, the output
stage is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
low level while S
FUNCTION TABLE
ADDRESS
Each mode is summarized in the function table.
A read cycle is executed by setting W at a high level and OE at a
A write cycle is executed whenever the low level W overlaps with
S
BLOCK DIAGRAM
X
H
L
L
L
INPUTS
1
* Pin numbers inside dotted line show those of TSOP
S
L
X
H
H
H
2
A11
A12
A14
A16
A15
A13
A10
A8
A9
A0
A1
A2
A3
A4
A5
A6
A7
W
X
X
L
H
H
10
31
28
12
11
23
27
26
25
4
8
7
6
5
3
2
9
1
and the high level S
1
OE
and S
X
X
X
L
H
16
15
14
13
12
11
10
20
19
18
17
31
2
7
4
3
1
Non selection
Non selection High-impedance
*
2
are in an active state(S
Mode
Write
Read
2
. The address must be set up
High-impedance
High-impedance
Dout
Din
1
DQ
,S
2
,W and OE.
1
=L,S
131072 WORDS
(512 ROWS
X128 COLUMNS
2
X 16BLOCKS)
=H).
GENERATOR
X 8 BITS
Stand-by
Stand-by
Active
Active
Active
CLOCK
1
I
CC
or S
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
2
MITSUBISHI
ELECTRIC
,
M5M51008CP,FP,VP,RV,KV,KR -55H, -70H,
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S
stand-by current which is specified as I
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the non-
selected mode.
When setting S
1
and S
2
. The power supply current is reduced as low as the
1
at a high level or S
2
at a low level, the chip are in
CC3
*
MITSUBISHI LSIs
or I
21
22
23
25
26
27
28
29
30
32
24
5
6
8
CC4
, and the memory
13
14
15
17
18
19
20
29
32
16
21
22
30
24
-55X, -70X
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
W
S1
S2
OE
V
GND
(0V)
CC
WRITE
CONTROL
INPUT
OUTPUT
ENABLE
INPUT
CHIP
SELECT
INPUTS
DATA
INPUTS/
OUTPUTS
2