PSD835F1-12B81 ST Microelectronics, PSD835F1-12B81 Datasheet
PSD835F1-12B81
Related parts for PSD835F1-12B81
PSD835F1-12B81 Summary of contents
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... FEATURES SUMMARY 5 V±10% Single Supply Voltage Mbit of Primary Flash Memory (8 uniform sectors) 256Kbit Secondary Flash Memory (4 uniform sectors Kbit SRAM Over 3,000 Gates of PLD: DPLD and CPLD 52 Reconfigurable I/O ports Enhanced JTAG Serial Port Programmable power management High Endurance: – ...
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... The PSD8XX series of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a Introduction simple and flexible solution for embedded designs. PSD8XX devices combine many of the peripheral functions found in MCU based applications: • 4 Mbit of Flash memory • ...
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... MCU address limit. • Separate program and data space – How can I write to flash memory while it resides in “program” space during field firmware updates, my 80C51 won’t allow it The flash PSD provides means to “reclassify” flash memory as “data” space during IAP, then back to “ ...
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... Zilog Z80, Z8 and Z180 • Infineon C500 family 4 Mbit Flash memory. This is the main Flash memory divided into eight equal-sized blocks that can be accessed with user-specified addresses. Internal secondary 256 Kbit Flash boot memory divided into four equal-sized blocks that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. 64 Kbit SRAM. The SRAM’ ...
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... EXT CS to PORT (CPLD) 16 OUTPUT MICRO CELLS PORT A & INPUT MICRO CELLS PORT A ,B & C CLKIN GLOBAL PLD, CONFIGURATION JTAG CONFIG. & & FLASH MEMORY SERIAL SECURITY CHANNEL LOADER 4 MBIT MAIN FLASH MEMORY 8 SECTORS POWER MANGMT 256 KBIT SECONDARY ...
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... The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each sector is individually selectable. The 64 Kbit SRAM is intended for use as a scratchpad memory extension to the microcontroller SRAM external battery is connected to the PSD8XX’s Vstby pin, data will be retained in the event of a power failure. ...
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... Flash memory, or SRAM. Since this is a sizable separate block, the application can also continue to operate. The secondary Flash boot memory can be programmed the same way by executing out of the main Flash memory. Table 4 indicates which programming methods can program different functional blocks of the PSD8XX ...
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... The designer does not need to enter Hardware Definition Language (HDL) System equations (unless desired) to define PSD pin functions and memory map information. The general design flow is shown in Figure 2 below. PSDsoft is available from our web site (www.st.com/psm) or other distribution channels. ...
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PSD8XX Family 6.0 The following table describes the pin names and pin functions of the PSD835G2. Pins that have multiple names and/or functions are defined using PSDsoft. Table 5. PSD835G2 Pin Descriptions Pin Name ADIO0-7 ADIO8-15 CNTL0 CNTL1 CNTL2 Reset ...
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PSD835G2 Table 5. PSD835G2 Pin Pin Name Pkg.) Descriptions PA0-PA7 51-58 (cont.) PB0-PB7 61-68 PC0-PC7 41-48 PD0 PD1 PD2 PD3 PE0 PE1 PE2 Pin* (TQFP Type I/O Port A, PA0-7. This port is pin configurable and has multiple CMOS functions: ...
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PSD8XX Family Table 5. PSD835G2 Pin Pin Name Pkg.) Descriptions PE3 (cont.) PE4 PE5 PE6 PE7 PF0-PF7 PG0-PG7 21-28 GND Pin* (TQFP Type 74 I/O Port E, PE3. This port is pin configurable and has multiple CMOS ...
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... Flash Boot Sector Protection C7 Enables JTAG Port Power Management B0 Register 0 Power Management B4 Register 2 E0 Page Register Places PSD memory areas in Program and/or E2 Data space on an individual basis. Read only – Flash and F0 SRAM size Read only – Boot type F1 and size 11 ...
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PSD8XX Family 8.0 All the registers in the PSD835G2 are included here for reference. Detail description of the registers are found in the Functional Block section of the Data Sheet. Register Bit Definition Data In Registers – Port A, B, ...
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PSD835G2 Input Micro Cells – Ports A, B and C 8.0 Register Bit Bit 7 Definition IMcell7 (cont.) Bit definitions: Read Only Registers Read Input Micro Cell[7:0] status on Ports A, B and C. Output Micro Cells A Register Bit ...
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PSD8XX Family 8.0 JTAG Enable Register Register Bit Bit 7 Definition * (cont.) Bit definitions: JTAG_Enable 1 = JTAG Port is Enabled. Page Register Bit 7 Pgr7 Bit definitions: Configure Page input to PLD. Default Pgr[7:0] = 00. PMMR0 Register ...
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... S_size[3:0] = 1h, SRAM size is 16K bit. S_size[3:0] = 3h, SRAM size is 64K bit. Memory_ID1 Register Bit Not used bit should be set to zero. Bit definitions: B_size[3:0] = 0h, Boot block size is 0K bit. B_size[3:0] = 2h, Boot block size is 256K bit. B_type[1:0] = 0h, Boot block is Flash memory. Bit 6 Bit 5 Bit 4 FL_data * * Bit 6 Bit 5 Bit 4 ...
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... Secondary Flash memory sectors have a Select signal (CSBOOT0-3) which can contain up to three product terms. Having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. When using a microcontroller (80C51) with separate Program and Data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other before and after IAP ...
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... Pin PE4 can be used to output the Ready/Busy status of the PSD835G2. The output on the pin will be a ‘0’ (Busy) when Flash memory blocks are being written to, or when the Flash memory block is being erased. The output will be a ‘1’ (Ready) when no write or erase operation is in progress ...
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... ROM device. However, Flash memory can only be erased and programmed with specific instructions. For example, the microcontroller cannot write a single byte directly to Flash memory as one would write a byte to RAM. To program a byte into Flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event ...
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... Don’t Care Address of the memory location to be read Data read from location RA during read operation Address of the memory location to be programmed. Addresses are latched on the falling edge of the WR# (CNTL0) pulse Data to be programmed at location PA. Data is latched o the rising edge of WR# (CNTL0) pulse. ...
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... Main Flash and secodary Flash memories are placed in the read array mode after power-up, chip reset Reset Flash instruction (see Table 8). The microcontroller can read the memory contents of main Flash or secondary Flash by using read operations any time the read operation is not part of an instruction sequence. ...
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... When the internal cycle is complete, the toggling will stop and the data read on the Data Bus D0-7 is the addressed memory location. The device is now accessible for a new Read or Write operation. The operation is finished when two successive reads yield the same output data ...
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... The PSD835G2 main Flash and secondary Flash memories require the MCU to send an instruction to program a word or perform an erase function (see Table 8). Once the MCU issues a Flash memory program or erase instruction, it must check for the status of completion. The embedded algorithms that are invoked inside the PSD835G2 support several means to provide status to the MCU ...
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PSD835G2 The Figure 4. Data Polling Flow Chart PSD835G2 Functional Blocks (cont.) 9.1.1.7.2 Data Toggle Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or Erase instruction is in progress or has completed. Figure ...
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PSD8XX Family The 9.1.1.7.2 Data Toggle PSD835G2 It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the word that was written to Flash with Functional the word ...
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... Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section 9.1.1.7. The Error bit (DQ5) returns a ‘1’ if there has been an Erase Failure (maximum number of erase cycles have been executed) ...
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... Specific Features 9.1.1.10.1 Main Flash and Secondary Flash Sector Protect Each sector of main Flash and secondary Flash memory can be separately protected against Program and Erase functions. Sector Protection provides additional data security because it disables all program or erase operations. This mode can be activated (or deactivated) through the JTAG-ISP Port or a Device Programmer ...
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... Flash memory will take µSeconds to return to Read Mode recommended that the reset pulse (except power on reset, see Reset Section least 25 µSeconds such that the Flash memory will always be ready for the MCU to fetch the boot code after reset is over. ...
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... SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) will automatically address Boot memory segment 0. Any address greater than 9FFFh will access the Flash memory segment 0. You can see that half of the Flash memory segment 0 and one-fourth of Boot segment 0 can not be accessed in this example ...
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... For example, you may wish to have SRAM and main Flash in Data Space at boot, and secondary Flash memory in Program Space at boot, and later swap main and secondary Flash memory. This is easily done with the VM register by using PSDsoft to configure it for boot up and having the microcontroller change it when desired. ...
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... Functional Code memory space is separated from data memory space. For example, the PSEN Blocks signal is used to access the program code from the main Flash Memory, while the RD signal is used to access data from the secondary Flash memory, SRAM and I/O Ports. (cont.) This configuration requires the VM register to be set to 0Ch. ...
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... Flash Memory, secondary Flash memory, and SRAM chip select (cont.) equations. If memory paging is not needed not all 8 page register bits are needed for memory paging, then these bits may be used in the PLD for general logic. See Application Notes. ...
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... The 9.1.5 Memory ID Registers PSD835G2 The 8-bit read only memory status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 Functional and Memory ID1 registers. The content of the registers are defined as follow: ...
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... The PLDs are briefly discussed in the next few paragraphs, and in more detail in sections 9.2.1 and 9.2.2. Figure 10 shows the configuration of the PLDs. The DPLD performs address decoding for internal components, such as memory, registers, and I/O port selects. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic ...
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... DIRECT MICRO CELL INPUT TO MCU DATA BUS INPUT MICRO CELL & INPUT PORTS 24 12 PORT D AND F INPUTS 8 FLASH MEMORY SELECTS 4 FLASH BOOT MEMORY SELECTS 1 SRAM SELECT 1 CSIOP SELECT 2 PERIPHERAL I/O MODE SELECTS 1 JTAG SELECT DIRECT MICRO CELL ACCESS FROM MCU DATA BUS ...
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... The DPLD, shown in Figure 11, is used for decoding the address for internal and external (cont.) components. The DPLD can generate the following decode signals: • 8 sector selects for the main Flash memory (three product terms each) • 4 sector selects for the Flash Boot memory (three product terms each) • ...
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... Additional address lines can be brought into PSD via Port (8) 3 ( (4) 3 (1) 3 (3) (1) 3 (1) CSBOOT 0 CSBOOT 1 4 SECONDARY FLASH MEMORY CSBOOT 2 SECTOR SELECTS CSBOOT 3 FS0 8 FLASH MEMORY SECTOR SELECTS FS7 RS0 SRAM SELECT CSIOP I/O DECODER SELECT PSEL0 PERIPHERAL I/O MODE SELECT PSEL1 JTAGSEL ...
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PSD835G2 Beta Information Figure 12. The Micro Cell and I/O Port BUS INPUT PLD MUX MUX ARRAY AND BUS INPUT PLD PSD8XX Family MUX MUX 37 ...
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PSD8XX Family The 9.2.2.1 Output Micro PSD835G2 Eight of the Output Micro Cells are connected to Port A pins are named as McellA0-7. The other eight Micro Cells are connected to Port B pins are named as McellB0-7. Functional Blocks ...
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... This is called product term expansion. PSDsoft will perform this expansion as needed. 9.2.2.3 Loading and Reading the Output Micro Cells (OMCs) The OMCs occupy a memory location in the MCU address space, as defined by the CSIOP (refer to the I/O section). The flip-flops in each of the 16 OMCs can be loaded from the data bus by a microcontroller ...
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PSD8XX Family The Figure 13. CPLD Output Micro Cell PSD835G2 Functional Blocks (cont.) 40 PSD835G2 ARRAY AND BUS INPUT PLD ...
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PSD835G2 The 9.2.2.6 Input Micro Cells (IMCs) PSD835G2 The CPLD has 24 IMCs, one for each pin on Ports A, B, and C. The architecture of the IMC is shown in Figure 14. The IMCs are individually configurable, and can ...
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PSD8XX Family The Figure 15. Handshaking Communication Using Input Micro Cells PSD835G2 Functional Blocks (cont.) MASTER MCU 9.2.2.7 External Chip Select The CPLD also provides eight chip select outputs that can be used to select external devices. The chip selects ...
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PSD835G2 The 9.3 Microcontroller Bus Interface PSD835G2 The “no-glue logic” PSD835G2 Microcontroller Bus Interface can be directly connected to most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their Functional bus types and control signals are shown in ...
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PSD8XX Family The Figure 17. An Example of a Typical 8-Bit Multiplexed Bus Interface PSD835G2 Functional Blocks (cont.) MICRO- CONTROLLER RESET Figure 18. An Example of a Typical 8-Bit Non-Multiplexed Bus Interface CONTROLLER RESET 7 ...
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... Figure 19 shows the interface to the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The microcontroller control signals PSEN, RD, and WR may be used for accessing the internal memory components and I/O Ports. The ALE input (pin PD0) latches the address. ...
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PSD8XX Family The Table 15. 80C251 Configurations PSD835G2 Configuration Functional Blocks (cont.) 9.3.3.3 80C51XA The Philips 80C51XA microcontroller family supports 16-bit multiplexed bus that can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are ...
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PSD835G2 Figure 19. Interfacing the PSD835G2 with an 80C31 19 X1 CRYSTAL RESET RESET 12 INT0 13 INT1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 P1.6 8 ...
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PSD8XX Family Figure 20. Interfacing the PSD835G2 to the 80C251, with One Read Input U1 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 CRYSTAL P3.0/RXD 13 P3.1/TXD ...
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PSD835G2 Figure 21. Interfacing the PSD835G2 to the 80C251, with Read and PSEN Inputs 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 CRYSTAL P3.0/RXD 13 P3.1/TXD 14 ...
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PSD8XX Family Figure 22. Interfacing the PSD835G2 to the 80C51XA, 8-Bit Data Bus 21 XTAL1 CRYSTAL 20 XTAL2 11 RXD0 13 TXD0 6 RXD1 7 TXD1 9 T2EX RESET 10 RST 14 INT0 ...
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PSD835G2 Figure 23. Interfacing the PSD835G2 with a 68HC11 34 PA0 33 PA1 32 PA2 31 PA3 30 PA4 29 PA5 28 PA6 27 PA7 8 XT CRYSTAL IRQ 18 XIRQ 20 PD0 21 PD1 22 PD2 ...
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PSD8XX Family The 9.4 I/O Ports PSD835G2 There are seven programmable I/O ports: Ports and G. Each of the ports is eight bits except Port D, which is 4 bits. Each port pin is ...
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DATA OUT REG ADDRESS D Q ALE G MICRO CELL OUTPUTS EXT CS READ MUX P D DATA IN B CONTROL REG DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD ...
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PSD8XX Family The 9.4.2 Port Operating Modes PSD835G2 The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the microcontroller writing to the Registers in CSIOP space, and some Functional by both. The ...
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PSD835G2 The Table 17. Port Operating Mode Settings PSD835G2 Functional Blocks Mode (cont.) MCU I/O PLD I/O Data Port (Port F) Address Out (Port Address In (Port A,B,C,D,F) for input Peripheral I/O (Port F) JTAG ISP (Note ...
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... MCU at run-time. See Table 18 for the address output pin assignments on Ports E, F and F for various MCUs. Note: Do not drive address lines with Address Out Mode to an external memory device intended for the MCU to boot from the external device. The MCU must first boot from PSD memory so the Direction and Control register bits can be set ...
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PSD835G2 The Figure 25. Peripheral I/O Mode PSD835G2 Functional Blocks (cont.) 9.4.3 Port Configuration Registers (PCRs) Each port has a set of PCRs used for configuration. The contents of the registers can be accessed by the microcontroller through normal read/write ...
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PSD8XX Family The 9.4.3.1 Control Register PSD835G2 Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode, and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. ...
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PSD835G2 The 9.4.3.3 Drive Select Register PSD835G2 The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should Functional ...
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PSD8XX Family The 9.4.4 Port Data Registers PSD835G2 The Port Data Registers, shown in Table 24, are used by the microcontroller to write data to or read data from the ports. Table 24 shows the register name, the ports having ...
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PSD835G2 The 9.4.5 Ports A, B and C – Functionality and Structure PSD835G2 Ports A and B have similar functionality and structure, as shown in Figure 26. The two ports can be configured to perform one or more of the ...
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PSD8XX Family The 9.4.6 Port D – Functionality and Structure PSD835G2 Port D has four I/O pins. See Figure 27. Port D can be configured to program one more of Functional the following functions: Blocks MCU I/O Mode (cont.) CPLD ...
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PSD835G2 The 9.4.8 Port F – Functionality and Structure PSD4000 Port F can be configured to perform one or more of the following functions: Functional MCU I/O Mode Blocks CPLD Output – external chip select ECS[7:0] can be connected to ...
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... The PSD835G2 offers configurable power saving options. These options may be used individually or in combinations, as follows: Functional Blocks All memory types in a PSD (Flash, Secondary Flash, and SRAM) are built with Zero-Power technology. In addition to using special silicon design methodology, (cont.) Zero-Power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory “ ...
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... Typical current consumption assuming no PLD inputs are changing state and Ports Pin Level No Change No Change Undefined Three-State Three-State Down Mode PLD Memory Propagation Access Delay Time Normal tpd No Access (Note 1) mode is based only on the Turbo Bit. the PLD Turbo bit is off. ...
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PSD8XX Family The Figure 29. APD Logic Block PSD835G2 Functional Blocks APD EN PMMR0 BIT 1=1 (cont.) ALE RESET CSI CLKIN Figure 30. Enable Power Down Flow Chart 66 TRANSITION DETECTION PD CLR APD COUNTER EDGE PD DETECT DISABLE MAIN ...
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PSD835G2 The Table 27. Power Management Mode Registers (PMMR0, PMMR2)** PSD835G2 PMMR0 Functional Bit 7 Blocks * (cont.) *** Bits and 7 are not used, and should be set to 0. *** The PMMR0, and PMMR2 register ...
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... Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal selects and enables the internal Flash, Boot Block, SRAM, and I/O for read or write operations involving the PSD835G2. A high on the CSI pin will disable the Flash memory, Boot Block, and SRAM, and reduce the PSD power consumption. However, the PLD and I/O pins remain operational when CSI is high ...
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... PSD835G2 remains in the reset state for an additional tOPR (maximum 120 ns) nanoseconds before the first memory access is allowed. The PSD835G2 Flash memory is reset to the read array mode upon power up. The FSi and CSBOOTi select signals along with the write strobe signal must be in the false state during power-up reset for maximum security of the data contents and to remove the possibility of data being written on the first edge of a write strobe signal ...
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... Reset of Flash Erase and Programming Cycles An external reset on the RESET pin will also reset the internal Flash memory state machine. When the Flash is in programming or erase mode, the RESET pin will terminate the programming or erase operation and return the Flash back to read mode in tNLNH-A (minimum 25 µ ...
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PSD835G2 The 9.6.1 Standard JTAG Signals PSD835G2 The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are Functional inputs, waiting ...
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... TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be high when the PSD835G2 device is in read array mode (Flash memory and Boot Block contents can be read). TSTAT will be low when Flash memory programming or erase cycles are in progress, and also when data is being written to the Flash Boot Block. ...
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PSD835G2 10.0 Symbol Absolute T STG Maximum Ratings NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device ...
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... PSD8XX is in each mode. Also, the supply power is considerably different if the Turbo bit is "OFF". The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figures 32 and 32a show the PLD mA/MHz as a function of the number of Product Terms (PT) used. ...
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PSD835G2 AC/DC Figure 30a. PLD I Parameters (cont.) Example of PSD835G2 Typical Power Calculation at V Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes ...
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PSD8XX Family AC/DC Example of Typical Power Calculation at V Parameters Conditions (cont.) Highest Composite PLD input frequency MCU ALE frequency (Freq ALE) Operational Modes Number of product terms used Turbo Mode Calculation (typical numbers used) I total = Ipwrdown ...
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PSD835G2 PSD835G2 DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis ...
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PSD8XX Family PSD835G2 AC/DC Parameters – GPLD Timing Parameters (5 V ± 10% Versions) GPLD Combinatorial Timing Symbol Parameter GPLD Input Pin/Feedback GPLD Combinatorial Output t GPLD Input to GPLD EA Output Enable t GPLD Input to ...
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PSD835G2 PSD835G2 AC/DC Parameters – GPLD Timing Parameters (5 V ± 10% Versions) GPLD Micro Cell Asynchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f Internal Feedback MAXA ( f ) CNTA Maximum Frequency Pipelined Data ...
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PSD8XX Family Microcontroller AC Symbols for PLD Timing. Interface – Example: AC/DC Parameters Signal Letters (5V ± 10% Versions) A – Address Input C – CEout Output D – Input Data E – E Input I – Interrupt Input L ...
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PSD835G2 Microcontroller Interface – PSD835G2 AC/DC Parameters (5V ± 10% Versions) Read Timing (5 V ± 10% Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid ...
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... Assuming data is stable before active write signal. 5. Assuming write is active before data becomes valid Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory. WHAX2 6ns when writing to the Output Micro Cell Registers AB and BC. ...
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PSD835G2 Microcontroller Interface – PSD835G2 AC/DC Parameters (5V ± 10% Versions) Port F Peripheral Data Mode Read Timing Symbol Parameter t Address Valid to Data Valid AVQV (PF) t CSI Valid to Data Valid SLQV (PF Data Valid ...
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PSD8XX Family Microcontroller Interface – PSD835G2 AC/DC Parameters (5V ± 10% Versions) Power Down Timing (5 V ± 10%) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD Enable t to Internal PDN Valid Signal ...
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PSD835G2 Microcontroller Interface – PSD835G2 AC/DC Parameters (5V ± 10% Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase t Sector Erase (Preprogrammed to 00) WHQV3 t ...
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PSD8XX Family PSD835G2 DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin ...
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PSD835G2 PSD835G2 AC/DC Parameters – CPLD Timing Parameters (3 3.6 V Versions) GPLD Combinatorial Timing (3 3.6 V Versions) Symbol Parameter GPLD Input Pin/Feedback GPLD Combinatorial Output GPLD Input to GPLD Output t ...
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PSD8XX Family PSD835G2 AC/DC Parameters – GPLD Timing Parameters (3 3.6 V Versions) GPLD Micro Cell Asynchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAXA Internal Feedback ( f Maximum Frequency Pipelined Data ...
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PSD835G2 Microcontroller AC Symbols for PLD Timing. Interface – Example: PSD835G2 AC/DC Signal Letters Parameters A – Address Input C – CEout Output (3 3.6 V Versions) D – Input Data E – E Input G – Internal ...
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PSD8XX Family Microcontroller Interface – PSD835G2 AC/DC Parameters (3 3.6 V Versions) Read Timing (3 3.6 V Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time ...
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... WR timing has the same timing as E and DS signals. 4. Assuming data is stable before active write signal. 5. Assuming write is active before data becomes valid Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory. WHAX2 t 7. ...
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PSD8XX Family Microcontroller Interface – PSD835G2 AC/DC Parameters (3 3.6 V Versions) Port F Peripheral Data Mode Read Timing Symbol Parameter t Address Valid to Data Valid AVQV (PF) t CSI Valid to Data Valid SLQV (PF) RD ...
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PSD835G2 Microcontroller Interface – PSD835G2 AC/DC Parameters (3 3.6 V Versions) Power Down Timing (3 3.6 V Versions) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD Enable t CLWH to ...
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PSD8XX Family Microcontroller Interface – PSD835G2 AC/DC Parameters (3 3.6 V Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed to 00) (Note 1) Flash Bulk Erase t Sector Erase (Preprogrammed to ...
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PSD835G2 Figure 33. Read Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV * t and t are not required 80C51XA in Burst Mode. AVLX LXAX * t AVLX ...
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PSD8XX Family Figure 34. Write Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t ...
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PSD835G2 Figure 35. Peripheral I/O Read Timing ALE/AS ADDRESS A/D BUS CSI RD Figure 36. Peripheral I/O Write Timing ALE /AS ADDRESS BUS WR DATA VALID t AVQV ( PF) t SLQV ( PF) t RLQV ( ...
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PSD8XX Family Figure 37. Combinatorial Timing – PLD CPLD INPUT CPLD OUTPUT Figure 38. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT PSD835G2 ...
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PSD835G2 Figure 39. Asynchronous Clock Mode Timing (Product-Term Clock) CLOCK INPUT REGISTERED OUTPUT Figure 40. Input Micro Cell Timing (Product-Term Clock) PT CLOCK INPUT OUTPUT tCHA tCLA tSA tHA t t INH INL PSD8XX Family tCOA ...
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PSD8XX Family Figure 41. Input to Output Disable/ Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Figure 42. Asynchronous Reset/ Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 43. ISC Timing TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO 100 tER tARPW tARP t ISCCH t ...
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PSD835G2 Figure 44. Reset Timing OPERATING LEVEL V CC RESET Figure 45. Key to Switching Waveforms WAVEFORMS t NLNH– OPR POWER ON RESET INPUTS STEADY INPUT MAY CHANGE FROM MAY CHANGE FROM ...
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PSD8XX Family 14 ° MHz A Pin Capacitance Symbol OUT C VPP NOTES: 1. These parameters are only sampled and are not 100% tested. 15.0 Figure 46. AC Testing Input/Output Waveform ...
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PSD835G2 18.0 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PSD835G2 Pin No. Pin 1 Assignments ...
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PSD8XX Family 19.0 Figure 48. Drawing U5 – 80-Pin Plastic Thin Quad Flatpack (TQFP) PSD835G2 Package Information PD2 PD3 AD0 AD1 AD2 AD3 AD4 GND V CC AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 104 (Package ...
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PSD835G2 Figure 48A. Drawing U5 – 80-Pin Plastic Thin Quad Flatpack (TQFP) (Package Type Index 3 Mark B Family: Plastic Thin Quad Flatpack (TQFP) Symbol Min 0° A – A2 0.95 B 0.17 ...
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... PSD834F2 8-bit PSD833F2 8-bit I/O Memory Other Ports Flash Program Store ISP via JTAG 2nd Flash Array IAP via MCU EEPROM Zero Power SRAM Per. Mode w/BB 52 4096Kb 256Kb – 64Kb – 27 1024Kb 256Kb – ...
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PSD835G2 21.0 Part Number Flash PSD Part Number Construction Construction CHARACTER # 1 PART NUMBER PSD BRAND NAME PSD = Standard Low Power Device FAMILY/SERIES 8 = Flash PSD for 8-bit MCUs 41 = Flash PSD for 16-bit MUCs (with ...
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... Page 82: changed tLXAX -70 Min from changed tDVWH -70 Min from 12 to 25, changed tWLWH -70 Min from 25 to 28. Page 83: changed Turbo Off from add 10 to add 12. PSD835G2: Configurable Memory System on a Chip for 8-Bit Microcontrollers Front page, and back two pages format, added to the PDF file 31-Jan-2002 1.2 ...
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...