M36W432BG ST Microelectronics, M36W432BG Datasheet - Page 8

• Manufacturer Part Number: M36W432BG
• Description: 32 Mbit 2Mb x16 / Boot Block Flash Memory and 4 Mbit 256Kb x16 SRAM / Multiple Memory Product
• Manufacturer: ST Microelectronics

M36W432TG, M36W432BG
SIGNAL DESCRIPTION
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A17). Addresses
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (
Enable (W
through two Chip Enable signals (E1
and the Write Enable signal (W
Address Inputs (A18-A20). Addresses A18-A20
are inputs for the Flash component only. The
Flash memory is accessed through the Chip En-
able (E
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (E
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
able is at V
tive mode. When Chip Enable is at V
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
stand-by level.
Flash Output Enable (G
controls data outputs during the Bus Read opera-
tion of the memory.
Flash Write Enable (
controls the Bus Write operation of the Flash
memory’s Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable, E
curs first.
Flash Write Protect (WP
input that gives an additional hardware protection
for each block. When Write Protect is at V
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at V
can be locked or unlocked. (refer to Table 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RP
hardware reset of the Flash memory. When Reset
is at V
are high impedance and the current consumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at V
in normal operation. Exiting reset mode the device
enters read array mode, but a negative transition
8/66
IH
IL
F
, the memory is in reset mode: the outputs
, the Lock-Down is disabled and the block
) and Write Enable (W
F
F
IL
, or Write Enable, W
) signals, while the SRAM is accessed
and Reset is at V
F
). The Reset input provides a
W
F
F
). The Chip Enable input
). The
F
F
). The Output Enable
). Write Protect is an
IH
F
S
) signals
the device is in ac-
).
F
, whichever oc-
IH
Write
, the device is
E
F
S
) and Write
and E2
A0-A17
Enable
IH
IL
, the
the
S
)
of Chip Enable or a change of the address is re-
quired to ensure valid data outputs.
SRAM Chip Enable (E1
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1
E2
power consumption to the standby level. E1
E2
SRAM memory array, while W
is not allowed to set E
at V
SRAM Write Enable (W
put controls writing to the SRAM memory array.
W
SRAM Output Enable (G
gates the outputs through the data buffers during
a read operation of the SRAM memory. G
tive low.
SRAM Upper Byte Enable (UB
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UB
SRAM Lower Byte Enable (LB
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LB
V
vides the power supply to the internal core of the
Flash Memory device. It is the main power supply
for all operations (Read, Program and Erase).
V
V
memory I/O pins and V
supply for the SRAM control pins. This allows all
Outputs to be powered independently of the Flash
core power supply, V
V
V
control input and a power supply pin for the Flash
memory. The two functions are selected by the
voltage range applied to the pin. The Supply Volt-
age V
can be applied in any order.
If V
V
age lower than V
against program or erase, while V
ables these functions (see Table 6, DC Character-
istics for the relevant values). V
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase,
however for Double or Quadruple Word Program
the results are uncertain.
If V
power supply pin. In this condition V
DDF
DDQF
DDQF
DDS
PPF
PPF
S
S
S
PPF
PPF
IH
is active low.
at V
can also be used to control writing to the
.
Program Supply Voltage. V
is seen as a control input. In this case a volt-
Supply Voltage (2.7V to 3.3V). V
DDF
at the same time.
and V
is kept in a low voltage range (0V to 3.6V)
provides the power supply for the Flash
is in the range 11.4V to 12.6V it acts as a
IL
and the Program Supply Voltage V
deselects the memory and reduces the
DDS
S
PPLK
S
is active low.
Supply Voltage (2.7V to 3.3V).
is active low.
gives an absolute protection
F
DDF
at V
S
S
DDS
, E2
). The Write Enable in-
S
. V
). The Output Enable
IL,
DDQF
S
provides the power
E1
S
). The Chip En-
S
S
remains at V
). The
S
). The
PPF
at V
can be tied to
PPF
PPF
PPF
S
> V
IL
is both a
at V
DDF
and E2
must be
is only
S
PP1
Upper
Lower
S
is ac-
IH
IL.
pro-
and
PPF
en-
or
It
S