M24256-A STMicroelectronics, M24256-A Datasheet - Page 9

• Manufacturer Part Number: M24256-A
• Description: 256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines
• Manufacturer: STMicroelectronics

Figure 8. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
internal address counter. The counter is then in-
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, with-
out acknowledging the byte output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
DEV SEL *
DEV SEL *
DEV SEL
DEV SEL
ACK
DATA OUT N
R/W
R/W
R/W
ACK
ACK
ACK
ACK
R/W
NO ACK
DATA OUT 1
BYTE ADDR
BYTE ADDR
DATA OUT
NO ACK
ACK
ACK
ACK
BYTE ADDR
BYTE ADDR
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
ACK
ACK
ACK
DATA OUT N
DEV SEL *
DEV SEL *
st
and 4
NO ACK
R/W
ACK
ACK
R/W
th
bytes) must be identical.
DATA OUT 1
DATA OUT
NO ACK
ACK
AI01105C
M24256-A
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