AT27LV1026-35 ATMEL Corporation, AT27LV1026-35 Datasheet - Page 2

• Manufacturer Part Number: AT27LV1026-35
• Description: 1-Megabit 2 x 32K x 16 16-Bit Interleaved Low-Voltage OTP EPROM
• Manufacturer: ATMEL Corporation

This device is internally architected as two 32K x 16 mem-
ory banks, odd and even. To begin a non-linear access
NLA cycle, (which typically equals a minimum of two linear
access LA cycles), ALE is asserted high and CS is
asserted low. The two internal 15-bit counters store the
address for the odd and even banks and increment alter-
nately during each subsequent linear access LA cycle. The
LA cycle will be terminated when CS is asserted high put-
ting the device in standby mode, or another NLA cycle
starts. The LA cycle can be resumed when CS is asserted
low and ALE stays low. The AT27LV1026 will continuously
output data within each LA cycle which is determined by
the read RD signal. Continuous interleave read operation is
possible as there is no physical limit to the linear access LA
output. When the last address in the array is reached the
counters will wrap around to the first address location and
continue.
For a NLA cycle where A0 = 0 (ALE asserted high, CS
asserted low), both even and odd counters will be loaded
with new address (A1 - A15). Outputs (O0 - O15) from the
even bank will be valid in t
outputs from the odd bank will become valid in t
the following LA cycle while the even counter increments
by one to ready the data out for the next LA cycle. The out-
puts will have even or odd data alternating and the
counters increment for the consecutive LA cycles until CS
is asserted high putting the device in standby mode, or a
new NLA cycle begins.
For a NLA cycle where A0 = 1 (ALE asserted high, CS
asserted low), the odd counter will be loaded with the new
address (A1 - A15) while the even counter gets loaded with
Operating Table
If A0 = 0 at beginning of NLA cycle:
and so on.
2
Consecutive
Cycle
NLA
LA
LA
LA
LA
Standby
LA
LA
AT27LV1026
Address
Even
+1
+1
+1
-
-
-
Counter
ACCNLA
Address from Even Bank
Odd
within the NLA cycle, the
+1
+1
+1
-
-
-
Outputs
from Odd Bank
from Even Bank
from Odd Bank
from Even Bank
HiZ
from Odd Band
from Even Bank
ACCLA
within
the new address+1. Outputs (O0 - O15) from odd bank of
memory will be valid in t
data output from the even bank of memory will become
valid in t
counter increments by one to ready the data out for the
next LA cycle. The outputs will have data from the odd or
even memory bank alternately and the counters increment
for the following consecutive LA cycles until CS is asserted
high putting the device in standby mode, or a new NLA
cycle begins. When coming out of standby mode, the
device can either enter into a new NLA cycle or resume
where the previous LA operation left off and was termi-
nated by standby mode.
System Considerations
Switching under active conditions may produce transient
voltage excursions. Unless accommodated by the system
design, these transients may exceed data sheet limits,
resulting in device non-conformance. At a minimum, a 0.1
capacitor should be utilized for each device. This capacitor
should be connected between the V
nals of the device, as close to the device as possible. Addi-
tionally, to stabilize the supply voltage level on printed cir-
cuit boards with large EPROM arrays, a 4.7 F bulk elec-
trolytic capacitor should be utilized, again connected
between the V
should be positioned as close as possible to the point
where the power supply is connected to the array.
If A0 = 1 at beginning of NLA cycle:
and so on.
Consecutive
Cycle
NLA
LA
LA
LA
LA
Standby
LA
LA
F high frequency, low inherent inductance, ceramic
ACCLA
within the following LA cycle while the odd
CC
Address+1
and Ground terminals. This capacitor
Even
+1
+1
+1
-
-
-
Counter
ACCNLA
Address
within the NLA cycle, the
Odd
+1
+1
+1
-
-
-
CC
and Ground termi-
Outputs
from Odd Bank
from Even Bank
from Odd Bank
from Even Bank
from Odd Bank
HiZ
from Even Bank
from Odd Band