93C56A Microchip Technology, 93C56A Datasheet - Page 5
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93C56A
Manufacturer Part Number
93C56A
Description
2K 5.0V Automotive Temperature Microwire Serial EEPROM
Manufacturer
Microchip Technology
Datasheet
1.93C56A.pdf
(12 pages)
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3.4
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. This cycle begins
on the rising clock edge of the last address bit.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
FIGURE 3-2:
FIGURE 3-3:
CLK
1998 Microchip Technology Inc.
DO
CLK
DO
CS
DI
CS
DI
CSL
ERASE
). DO at logical “0” indicates that program-
HIGH-Z
HIGH-Z
ERASE TIMING
ERAL TIMING
1
1
0
1
0
1
A
1
N
A
0
N
-1
A
Preliminary
X
N
-2
•••
•••
3.5
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle, except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the rising clock edge of the last address bit.
Clocking of the CLK pin is not necessary after the
device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
plete.
A0
X
T
T
CSL
CSL
CSL
Erase All (ERAL)
) and before the entire ERAL cycle is com-
T
T
EC
WC
T
T
SV
CHECK STATUS
SV
CHECK STATUS
BUSY
BUSY
93C56A/B
READY
READY
DS21206B-page 5
HIGH-Z
HIGH-Z
T
T
CZ
CZ