24LC65-IP MicrochipTechnology, 24LC65-IP Datasheet - Page 3

• Manufacturer Part Number: 24LC65-IP
• Description: 64K2.5VI2CSmartSerialEEPROM
• Manufacturer: MicrochipTechnology

TABLE 1-3:
FIGURE 1-2:
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition setup time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
Output fall time from V
V
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
Note 1: Not 100 percent tested. C
SDA
IN
SDA
OUT
SCL
1996 Microchip Technology Inc.
IL
max
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
3: The combined T
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
T
SU
High Endurance Block
Rest of Array
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
cache for total time.
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
:
STA
Parameter
T
AC CHARACTERISTICS
BUS TIMING DATA
SP
T
IH
AA
min to
SP
T
and V
F
T
HD
T
:
T
T
Symbol
T
T
T
LOW
STA
HYS
T
T
HD
SU
HD
SU
SU
F
T
T
B
T
T
T
HIGH
LOW
T
T
CLK
BUF
WR
OF
AA
SP
= total capacitance of one bus line in pF.
:
:
:
:
:
R
F
STA
DAT
DAT
STO
STA
specifications are due to new Schmitt trigger inputs which provide improved
Vcc = 2.5V-6.0V
4000
4700
4000
4700
4000
4700
T
10M
T
Min
250
1M
STD. MODE
—
—
—
—
—
—
—
HIGH
HD
0
:
DAT
1000
3500
Max
100
300
250
50
—
—
—
—
—
—
—
—
—
—
5
T
AA
20 + 0.1
V
FAST MODE
1300
1300
10M
CC
Min
600
600
600
100
600
1M
C
—
—
—
—
—
—
0
B
T
= 4.5-6.0V
SU
:
DAT
Max
400
300
300
900
250
—
—
—
—
—
—
—
—
50
—
—
5
T
SU
:
ms/page (Note 4)
STO
cycles
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
R
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for
repeated START condi-
tion
(Note 2)
Time the bus must be
free before a new trans-
mission can start
(Note 1), C
Note 3
25 C, Vcc = 5.0V, Block
Mode (Note 5)
24LC65
T
BUF
Remarks
DS21073E-page 3
B
100 pF