93AA46 Microchip Technology, 93AA46 Datasheet - Page 4

• Manufacturer Part Number: 93AA46
• Description: 1K/2K/4K 1.8V Microwire Serial EEPROM
• Manufacturer: Microchip Technology

93AA46/56/66
2.0
When the ORG pin is connected to V
nization is selected. When it is connected to ground,
the (x8) organization is selected.
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is nor-
mally held in a high-Z state except when reading data
from the device, or when checking the READY/BUSY
status during a programming operation. The ready/
busy status can be verified during an Erase/Write oper-
ation by polling the DO pin; DO low indicates that pro-
gramming is still in progress, while DO high indicates
the device is ready. The DO will enter the high-Z state
on the falling edge of the CS.
2.1
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero” that
precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
2.3
During power-up, all programming modes of operation
are inhibited until V
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
DS20067G-page 4
CC
has fallen below 1.4V at nominal conditions.
FUNCTIONAL DESCRIPTION
START Condition
DI/DO
Data Protection
CC
has reached a level greater than
CC
, the (x16) orga-
Instructions,
2.4
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable after
the specified time delay (T
sible when CS is held high. The memory data will auto-
matically cycle to the next register and output
sequentially.
2.5
The 93AA46/56/66 power up in the Erase/Write Disable
(EWDS) state. All programming modes must be pre-
ceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or V
accidental data disturb, the EWDS instruction can be
used to disable all Erase/Write functions and should fol-
low all programming operations. Execution of a READ
instruction is independent of both the EWEN and
EWDS instructions.
2.6
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The ERASE cycle takes 4 ms per word typical.
2.7
The WRITE instruction is followed by 16 bits (or by 8
bits) of data which are written into the specified
address. After the last data bit is put on the DI pin, CS
must be brought low before the next rising edge of the
CLK clock. This falling edge of CS initiates the self-
timed auto-erase and programming cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion.
The WRITE cycle takes 4 ms per word typical.
CC
CSL
CSL
is removed from the device. To protect against
READ
Erase/Write Enable and Disable
(EWEN,EWDS)
ERASE
WRITE
) and before the entire write cycle is complete.
). DO at logical “0” indicates that program-
1996 Microchip Technology Inc.
PD
). Sequential read is pos-