24LC080-IP MicrochipTechnology, 24LC080-IP Datasheet - Page 5

• Manufacturer Part Number: 24LC080-IP
• Description: 8K/16K2.5VSPIOBusSerialEEPROM
• Manufacturer: MicrochipTechnology

2.0
The 25LC080/160 is an 1024/2048 byte EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro-
controller families, including Microchip’s midrange
PIC16CXX microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly with soft-
ware.
The 25LC080/160 contains an 8-bit instruction register.
The part is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. If the WPEN bit in
the status register is set, the WP pin must be held high
to allow writing to the non-volatile bits in the status reg-
ister.
Table 2-1 contains a list of the possible instruction bytes
and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data is sampled on the first rising edge of SCK after CS
goes low. If the clock line is shared with other peripheral
devices on the SPI bus, the user can assert the HOLD
input and place the 25LC080/160 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
2.1
The 25LC080/160 contains a write enable latch. This
latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch. The following is
a list of conditions under which the write enable latch
will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
2.2
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
The Write-In-Process (WIP) bit indicates whether the
25LC080/160 is busy with a write operation. When set
to a ‘1’ a write is in progress, when set to a ‘0’ no write
is in progress. This bit is read only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array and status register, when set
to a ‘0’ the latch prohibits writes to the array and status
register. The state of this bit can always be updated via
WPEN
1996 Microchip Technology Inc.
7
PRINCIPLES OF OPERATION
Write Enable (WREN) and Write
Disable (WRDI)
Read Status Register (RDSR)
6 5 4
X X X
BP1
3
BP0
2
WEL
1
WIP
0
Preliminary
the WREN or WRDI commands regardless of the state
of write protection on the status register. This bit is read
only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.
The Write Protect Enable (WPEN) bit is a non-volatile
bit that is available as an enable bit for the WP pin. The
Write Protect (WP) pin and the Write Protect Enable
(WPEN) bit in the status register control the program-
mable hardware write protect feature. Hardware write
protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write protected, only writes
to non-volatile bits in the status register are disabled.
See Table 2-2 for matrix of functionality on the WPEN
bit and Figure 2-1 for a flowchart of Table 2-2.
TABLE 2-1:
See Figure 3-5 for RDSR timing sequence.
Instruction
WRITE
WREN
WRSR
RDSR
READ
WRDI
Name
Instruction
0000 0100
0000 0101
0000 0011
0000 0110
0000 0001
0000 0010
INSTRUCTION SET
Format
25LC080/160
latch (enable write
operations)
enable latch (disable
write operations)
(write protect enable
and block write pro-
tection bits)
memory array begin-
ning at selected
address
array beginning at
selected address
Set the write enable
Reset the write
Read status register
Write status register
Read data from
Write data to memory
Description
DS21145D-page 5