24LC00 MicrochipTechnology, 24LC00 Datasheet - Page 6

• Manufacturer Part Number: 24LC00
• Description: 128BitI2CBusSerialEEPROM
• Manufacturer: MicrochipTechnology

24xx00
6.0
6.1
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W bit
(which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24xx00. Only the lower
four address bits are used by the device, and the upper
four bits are don’t cares. The 24xx00 will acknowledge
the address byte and the master device will then trans-
mit the data word to be written into the addressed mem-
ory location. The 24xx00 acknowledges again and the
master generates a stop condition. This initiates the
internal write cycle, and during this time the 24xx00 will
not generate acknowledge signals (Figure 7-2). After a
byte write command, the internal address counter will
not be incremented and will point to the same address
location that was just written. If a stop bit is transmitted
to the device at any point in the write command
sequence before the entire sequence is complete, then
the command will abort and no data will be written. If
more than 8 data bits are transmitted before the stop bit
is sent, then the device will clear the previously loaded
byte and begin loading the data buffer again. If more
than one data byte is transmitted to the device and a
stop bit is sent before a full eight data bits have been
transmitted, then the write command will abort and no
data will be written. The 24xx00 employs a V
old detector circuit which disables the internal erase/
write logic if the V
24LC00) or 3.8V (24C00) at nominal conditions.
FIGURE 7-2:
DS21178A-page 6
SDA LINE
BUS ACTIVITY
MASTER
BUS ACTIVITY
X = Don’t Care Bit
WRITE OPERATIONS
Byte Write
S
T
A
R
T
S
BYTE WRITE
CC
1
0
is below 1.5V (24AA00 and
1
CONTROL
BYTE
0
X
X
X
0
CC
A
C
K
thresh-
X
Preliminary
X
X
ADDRESS
WORD
X
7.0
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for flow
diagram.
FIGURE 7-1:
ACKNOWLEDGE POLLING
A
C
K
Initiate Write Cycle
Send Control Byte
ACKNOWLEDGE POLLING
FLOW
Write Command
with R/W = 0
Acknowledge
Condition to
Send Stop
(ACK = 0)?
Send Start
Did Device
Operation
Send
Next
1996 Microchip Technology Inc.
DATA
YES
NO
A
C
K
P
S
T
O
P