Z89135 Zilog., Z89135 Datasheet - Page 50

• Manufacturer Part Number: Z89135
• Description: Low-Cost DTAD Controller
• Manufacturer: Zilog.

Z89135/136 (ROMless)
Low-Cost DTAD Controller
DSP IRQ0. This bit defines the source of DSP IRQ0 inter-
rupt.
D/A_Sampling Rate. This field defines the sampling rate
of the D/A output. It changes the period to Timer3 interrupt
and the maximum possible accuracy of the D/A (Table 16).
DSP0. DSP0 is a general-purpose output pin connected to
Bit 6. This bit has no special significance and may be used
to output data by writing to bit 6.
DSP1. DSP1 is a general-purpose output pin connected to
Bit 7. This bit has no special significance and may be used
to output data by writing to bit 7.
Enable A/D. Writing a 0 to this location disables the A/D
converter, a 1 will enable it. A hardware reset forces this
bit to be 0.
DSP TIMERS
Timer2 is a free running counter that divides the XTAL fre-
quency (20.48 MHz) to support different sampling rates for
the A/D converter. The sampling rate is defined by the An-
alog Control Register. Upon reaching the end of a count,
the timer generates an interrupt request to the DSP.
1-50
D/A_Sampling
1 0 0
0 1 0
0 1 1
0 0 1
Rate
Table 16. D/A Data Accuracy
D/A Accuracy
64 kHz
16 kHz
10 kHz
4 kHz
20.48 MHz
OSC
Sampling Rate
Figure 36. Timer2 and Timer3
10 Bits
10 Bits
10 Bits
8 Bits
P R E L I M I N A R Y
128, 64, 32, 16, 8 kHz
64, 16, 10, 4 kHz
TIMER2
TIMER3
Conversion Done. This Read Only flag indicates that the
A/D conversion is complete. Upon reading EXT5 (A/D da-
ta), the Conversion Done flag is cleared.
Start A/D Conversion. Writing a 1 to this location immedi-
ately starts one conversion cycle. If this bit is reset to 0 the
input data is converted upon successive Timer2 time-outs.
A hardware reset forces this bit to be 1.
A/D_Sampling Rate. This field defines the sampling rate
of the A/D. It changes the period of Timer2 interrupt (Table
17).
Analogous to Timer2, Timer3 generates the different sam-
pling rates for the D/A converter. Timer3 also generates an
interrupt request to the DSP upon reaching its final count
value (Figure 36).
A/D_Sampling Rate
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
Table 17. A/D Sampling Rate
A/D
D/A
ADC Sampling Rate
128 kHz
64 kHz
32 kHz
16 kHz
8 kHz
DS97TAD0300
Zilog