PGA4311K Burr-Brown Corporation, PGA4311K Datasheet - Page 8

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PGA4311K

Manufacturer Part Number
PGA4311K
Description
4 CHANNEL AUDIO VOLUME CONTROL
Manufacturer
Burr-Brown Corporation
Datasheet
PGA4311
SBOS230A – MARCH 2002 – REVISED JUNE 2002
SERIAL CONTROL PORT
The serial control port is utilized to program the gain set-
tings for the PGA4311. The serial control port includes
three input pins and one output pin. The inputs include
CS (pin 14), SDI (pin 13), and SCLK (pin 15). The sole
output pin is SDO (pin 16).
The CS pin functions as the chip select input. Data may
be written to the PGA4311 only when CS is LOW. SDI
is the serial data input pin. Control data is provided as
a 32-bit word at the SDI pin, 8 bits each for each chan-
nel gain setting.
Figure 2. Serial Interface Protocol.
8
0 is the Least Significant Bit of the Channel Gain Byte
7 is the Most Significant Bit of the Channel Gain Byte
Gain Byte Format is MSB First, Straight Binary
SDO transitions on the falling edge of SCLK.
SDI is latched on the rising edge of SCLK.
Data is formatted as MSB first, straight binary code.
SCLK is the serial clock input. Data is clocked into SDI
on the rising edge of SCLK.
SDO is the serial data output pin, and is used when
daisy-chaining multiple PGA4311 devices. Daisy-chain
operation is described in detail later in this section. SDO
is a tri-state output, and assumes a high impedance state
when CS is HIGH. Data appears at SDO on the falling
edge of SCLK.
The protocol for the serial control port is shown in
Figure 2. See Figure 3 for detailed timing specifi-
cations for the serial control port.
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