PDI1394L21BE Philips Semiconductors, PDI1394L21BE Datasheet
PDI1394L21BE
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PDI1394L21BE Summary of contents
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NOTICE: SEE ATTACHED ERRATA WHICH FOLLOWS THIS DOCUMENT FOR INFORMATION REGARDING CHANGED SPECIFICATIONS PDI1394L21 1394 full duplex AV link layer controller Preliminary specification Supersedes data of 1999 Mar 30 INTEGRATED CIRCUITS 1999 Aug 06 ...
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... It is available in the LQFP100 and TQFP100 packages. CONDITIONS MIN 3.0 Operating 49.147 OUTSIDE NORTH AMERICA PDI1394L21BE PDI1394L21BP NOTE: This datasheet is subject to change. 2 Preliminary specification PDI1394L21 TYP MAX UNIT 3.3 3 49.152 49.157 MHz NORTH AMERICA PKG. DWG. # PDI1394L21BE SOT407 AB15 PDI1394L21BP SOT386 BB2 ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 5.0 PIN CONFIGURATION 100 76 1 TQFP LQFP Pin Function Pin Function 1 HIF D7 35 PHY D6* 2 HIF D6 36 PHY D5* 3 HIF D5 37 PHY D4* 4 HIF D4 38 GND 5 GND PHY D3 HIF D3 ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 6.0 FUNCTIONAL DIAGRAM HIF A[8:0] HIF D[7:0] HIF WR_N HIF RD_N HIF CS_N HIF INT_N RESET_N CYCLEIN CYCLEOUT AV1 D[7:0] AV1CLK AV1VALID AV1SYNC AV1FSYNC AV1ENKEY AV1ENDPCK AV1ERR[1:0] 7.0 INTERNAL BLOCK DIAGRAM AV1 D[7:0] AV1CLK AV1SYNC AV1 LAYER AV1VALID ISOCHRONOUS ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 8.0 APPLICATION DIAGRAM MPEG OR DVC INTERFACE DECODER MPEG OR DVC INTERFACE DECODER DATA 8/ ADDRESS 9/ INTERRUPT & CONTROL HOST CONTROLLER 9.0 PIN DESCRIPTION 9.1 Host Interface PIN No. PIN SYMBOL I HIF D[7:0] I/O Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 9.2 AV Interface 1 NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register (0X018)—default is transmit. PIN No. PIN SYMBOL I/O 77, 76, 75, 74, AV1 D[7:0] I/O Audio/Video Data 7 (MSB) through 0. Byte-wide interface to the AV layer 1. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 9.4.1 Bushold and Link/PHY single capacitor galvanic isolation 9.4.1.1 Bushold The PDI1394L21 uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by a 3-Stated device or input coupling capacitor. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 9.5 Other Pins PIN No. PIN SYMBOL I/O These pins are reserved for factory testing. For normal operation they should be connected to 65, 66, 67 RESERVED NA ground. 51, 62, 100 N/C NA These pins should not be connected or terminated. Provides the capability to supply an external cycle timer signal for the beginning of 1394 bus ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 11.1 Buffer Memory Sizes Asynchronous Receive Response FIFO Asynchronous Receive Request FIFO Asynchronous Transmit Response FIFO Asynchronous Transmit Request FIFO Isochronous (AV) Transmit Buffer Isochronous (AV) Receive Buffer 12.0 FUNCTIONAL DESCRIPTION 12.1 Overview The PDI1394L21 is an IEEE 1394–1995 compliant link layer controller. It provides a direct interface between a 1394 bus and various MPEG–2 and DVC codecs ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 12.3 The host interface The host interface allows an 8 bit CPU to access all registers and the asynchronous packet queues specifically designed for an 8051 microcontroller but can also be used with other CPUs. There are 64 register addresses (for quadlet wide registers). To access bytes rather than quadlets the address spaces is 256 bytes, requiring 8 address lines ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 12.3.2 Write accesses To write to an internal register the host interface must collect the 4 byte values into a 32 bit value and then write the result to the target register in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is ready to be written to the actual target register. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 12.3.5 The CPU bus interface signals The CPU interface is directly compatible with an 8051 microcontroller. It uses a separate HIF RD_N and HIF WR_N inputs and a HIF CS_N chip select line, all of which are active LOW. There are 9 address inputs (HIF A0..HIF A8) and 8 data in/out lines HIF D0..HIF D7. An open drain HIF INT_N output is used to signal interrupts to the CPU ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 12.5 Link Packet Data Formats The data formats for transmission and reception of data are shown below. The transmit format describes the expected organization for data presented to the link at the asynchronous transmit, physical response, or isochronous transmit FIFO interfaces. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller Table 1. No-Data Transmit Format Field Name spd This field indicates the speed at which this packet sent. 00=100 Mbs, 01=200 Mbs, and 10=400 Mbs undefined tLabel This field is the transaction label, which is used to pair up a response packet with its corresponding request packet. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller Figure 9. Quadlet Read Response Transmit Format Table 2 ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 12.5.1.3 Block Transmit The block transmit format is shown below, this is the generic format for reads and writes. The first quadlet contains packet control information. The second and third quadlets contain the 16-bit destination node ID and either the 48-bit destination offset (for requests) or the response code and reserved data (for responses) ...
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... Philips Semiconductors 1394 full duplex AV link layer controller Table 3. Block Transmit Field Field Name spd, tLabel, rt, tCode, destinationID, destinationOffsetHigh, destinationOffsetLow, rCode dataLength extendedTcode block data padding 12.5.1.4 Unformatted Transmit The unformatted transmit format is shown in Figure 13. The first quadlet contains packet control information. The remaining quadlets contain data that is transmitted without any formatting on the bus ...
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... Philips Semiconductors 1394 full duplex AV link layer controller Table 5. Asynchronous Receive Fields Field Name destinationID This field is the concatenation of busNumbers (or all ones for “local bus”) and nodeNumbers (or all ones for broadcast) for this node. tLabel This field is the transaction label, which is used to pair up a response packet with its corresponding request packet. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 12.5.2.1 No-Data Receive The no-data receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlet contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for responses) ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 12.5.2.2 Quadlet Receive The quadlet receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlets contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for responses) ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 12.5.2.3 Block receive The block receive format is shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlets contain 16-bit sourceID and either the 48-bit destination offset (for requests) or the response code and reserved data (for responses) ...
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... Philips Semiconductors 1394 full duplex AV link layer controller Figure 20. Block Read or Lock Response Receive Format 12.5.2.4 Self-ID and PHY packets receive The self-ID and PHY packet receive formats are shown below. The first quadlet contains a synthesized packet header with a tCode of 0xE (hex) ...
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... Philips Semiconductors 1394 full duplex AV link layer controller For PHY packets, there is a single following quadlet which is the first quadlet of the PHY packet. The check quadlet has already been verified and is not included ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 12.5.3 Interrupts The PDI1394L21 provides a single interrupt line (HIF INT_N) for connection to a host controller. Status indications from four major areas of the device are collected and ORed together to activate HIF INT_N. Status from four major areas of the device are collected in four status registers; ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.0 REGISTER MAP Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the lower 8 bits, and leave the other bits unaffected (see Section 12.3.2 for more information). The values written to undefined fields/bits are ignored and thus DON’ ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 31 REGISTER ADDRESS IDREG BUS ID 0x000 LNKCTL BSYCTRL 0x004 LNKPHYINTACK 0x008 LNKPHYINTE 0x00C CYCLE_SECONDS CYCTM 0x010 PHYACS PHYRGAD 0x014 GLOBCSR 0x018 <RESERVED> 0x01C ITXPKCTL 0x020 ITXHQ1 0x024 ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 31 REGISTER ADDRESS ITXCTL 0x034 ITXMEM 0x038 <RESERVED> 0x03C IRXPKCTL 0x040 0 0 IRXHQ1 SID 0x044 IRXHQ2 FMT 0x048 IRXINTACK 0x04C IRXINTE 0x050 IRXCTL 0x054 IRXMEM 0x058 <RESERVED> 0x05C . . . <RESERVED> 0x07C 1999 Aug ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 31 REGISTER ADDRESS ASYCTL 0x080 ASYMEM 0x084 TX_RQ_NEXT 0x088 TX_RQ_LAST 0x08C TX_RP_NEXT 0x090 TX_RP_LAST 0x094 RREQ 0x098 RRSP 0x09C ASYINTACK 0x0A0 ASYINTE 0x0A4 <RESERVED> 0x0A8 . . . <RESERVED> 0x0F8 1999 Aug MAXRC TOS ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.1 Link Control Registers ID Register (IDREG) – Base Address: 0x000 13.1.1 The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset. 3130 ...
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... Philips Semiconductors 1394 full duplex AV link layer controller Bit 10: R/W Cycle Source (CYSOURCE): When asserted, the cycle_count field increments and the cycle_offset field resets for each positive transition of CYCLEIN. When deasserted, the cycle count field increments when the cycle_offset field rolls over. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’ to the bit corresponding to the interrupt desired. This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the bits enables that function to create an interrupt ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.1.7 Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018 This register is the top level interrupt status register. If the external interrupt line is set, this register will indicate which major portion of the AV Link generated the interrupt. There is no interrupt acknowledge required at this level. These bits auto clear when the interrupts in the appropriate section of the device are cleared or disabled ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.2 AV (Isochronous) Transmitter and Receiver Registers Isochronous 13.2.1 Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020 This register allows the user to set up the appropriate AV packets from data entered into the AV interface. The packing and control parameters (TRDEL, MAXBL, DBS, FN, QPC, and SPH) should never be changed while the transmitter is operating ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024 The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is included in Common Isochronous Packet (CIP) header quadlet 1. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter. Bits 2, 3, and 4 ”auto repair” themselves, i.e. AVLINK will detect the situation and attempt to recover on its own. The host controller still needs to clear these interrupts to be alerted the next time ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34 Reset Value 0x00000000 Bit 15..14: R/W Tag: Tag code to insert in isochronous bus packet header. Should be ‘01’ for IEC 61883 International Standard data. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040 NOTE: When receiver reset is required, first disable receiver (EN_IRX = 0), then wait until Rx FIFO is emptied, then perform the reset. This will allow previously received packets the application instead of being lost. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.2.9 Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044 This quadlet represents the last received header value when AV receiver is operating ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.2.12 Isochronous Receiver Interrupt Enable (IRXINTE) – Base Address: 0x050 Interrupt enable bits for AV Receiver Reset Value 0x00000000 Bit 10..0 are interrupt enable bits for the Isochronous Receiver Interrupt Acknowledge (IRXINTACK). 13.2.13 Isochronous Receiver Control Register (IRXCTL) – ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.2.14 Isochronous Receiver Memory Status (IRXMEM) – Base Address: 0x058 Reset Value 0x00000003 Bit 6: R IRM100LFT: FIFO is 100 quadlets from full. ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.3 Asynchronous Control and Status Interface 13.3.1 Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080 Reset Value 0x00300320 Bit 23: R/W DIS_BCAST: Disable the reception of broadcast packets ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) – Base Address: 0x088 Bit 31..0: W TX_RQ_NEXT: First/middle quadlet of packet for transmitter request queue (write only). ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098 3130 Reset Value 0x00000000 Bit 31..0: R RREQ:Quadlet of packet from receiver request queue (transfer register). ...
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... Philips Semiconductors 1394 full duplex AV link layer controller Bit 0: R/W TREQQWR: Transmitter request queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt. 13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4 Reset Value 0x00000000 Bits16..0 are interrupt enable bits for the Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK). ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 14.1 Pin Categories Table 11. Pin Categories Category 1: Category 2: Category 3: Input/Output Input Input HIF D[7:0] HIF A[8:0] RESET_N AVxSYNC HIF CS_N CYCLEIN AVxVALID HIF WR_N ISO_N AV xD[7:0] HIF RD_N AVxENKEY AVxENDPCK AVxCLK AVxFSYNC 15.0 AC CHARACTERISTICS GND = 0V 50pF L SYMBOL ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 16.0 TIMING DIAGRAMS 16.1 AV Interface Operation AVCLK MESSAGE AV D[7:0] AVSYNC AVVALID AVERR[0] ASSERTED IN THE EVENT OF A DATA BLOCK SEQUENCE ERROR AVERR[1] 16.2 AV Interface Critical Timings AVCLK É É É [7:0], AVVALID, É É É VALID AVSYNC, AVENDPCK ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 16.3 PHY-Link Interface Critical Timings SCLK PHY D[0:7], PHY CTL[0:1] Figure 28. PHY D[0:7], PHY CTL[0:1] Input Setup and Hold Timing Waveforms PHY D[0:7], PHY CTL[0:1], LREQ Figure 29. PHY D[0:7], PHY CTL[0:1], and LREQ Output-Delay Timing Waveforms 16.4 Host Interface Critical Timings ...
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... Philips Semiconductors 1394 full duplex AV link layer controller 16.5 CYCLEIN/CYCLEOUT Timings CYCLEIN SCLK CYCLEIN CYCLEOUT 16.6 RESET Timings RESET_N 1999 Aug 06 50% 50% 50 CWH CWL t CP Figure 31. CYCLEIN Waveform 50 50% Figure 32. CYCLEOUT Waveforms 50% 50% t RESET SV00698 Figure 33. RESET_N Waveform 48 Preliminary specification ...
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... Philips Semiconductors 1394 full duplex AV link layer controller TQFP100: plastic thin quad flat package; 100 leads; body 1.0 mm 1999 Aug 06 49 Preliminary specification PDI1394L21 SOT386-1 ...
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... Philips Semiconductors 1394 full duplex AV link layer controller LQFP100: plastic low profile quad flat package; 100 leads; body 1.4 mm 1999 Aug 06 50 Preliminary specification PDI1394L21 SOT407-1 ...
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... MHz the AVCLK signal which introduces the state of the ENKEY pin (and all others) to the AV port interface logic. Please consult Philips IEEE 1394 Applications Engineering Group (1394@philips.com) for use of this function at other AVCLK frequencies. Errata To the PDI1394L21 1394 Full Duplex AV Link Layer Controller (Data Sheet dated: 1999 August 6). Philips Semiconductors August 6, 1999 ...
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... Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no ...