DS5001FP-12-44 Dallas Semiconducotr, DS5001FP-12-44 Datasheet - Page 5

• Manufacturer Part Number: DS5001FP-12-44
• Description: 128k Soft Microprocessor Chip
• Manufacturer: Dallas Semiconducotr

33, 35,
71, 69,
67, 65,
61, 59,
57, 55
37
10
74
72
63
62
78
22
23
32
42
43
14
73
2
3
28, 26,
24, 23,
21, 20,
19, 18
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
37
29
33
22
40
9
BD7–0
MSEL
PROG
R/
CE1N
VRST
CE1
CE2
CE3
CE4
PE1
PE2
PE3
PE4
NC
PF
W
and A15 respectively.
Byte-Wide Data-Bus Bits 7–0. This 8-bit, bidirectional bus is combined with the
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed on
SRAM, and optionally to a real-time clock or other peripheral.
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide bus. It
is controlled by the memory map and partition. The blocks selected as program (ROM) are
write-protected.
Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-
wide bus. It connects to the chip enable input of one SRAM.
remains in a logic high inactive state when V
Non-battery-backed version of chip enable 1. This can be used with a 32kB EPROM. It
should not be used with a battery-backed chip.
Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts
into A16 for a 128k x 8 SRAM.
V
Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts
into A15 for a 128k x 8 SRAM.
V
Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It
connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused.
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when
the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-time clock
such as the DS1283.
below V
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when
the PES bit is set to a logic 1.
falls below V
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when
the PES bit is set to a logic 1.
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when
the PES bit is set to a logic 1.
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when V
Invokes the bootstrap loader on a falling edge. This signal should be debounced so that
only one edge is detected. If connected to ground, the micro enters bootstrap loading on
power-up. This signal is pulled up internally.
This I/O pin (open drain with internal pullup) indicates that the power supply (V
has fallen below the V
DS5001FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is
guaranteed even when V
low externally. This allows multiple parts to synchronize their power-down resets.
This output goes to a logic 0 to indicate that V
lithium backup. Because the micro is lithium-backed, this signal is guaranteed even when
V
isolate battery-backed functions from non-battery-backed functions.
Memory Select. This signal controls the memory size selection. When MSEL = +5V, the
DS5001FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5001FP expects to
use a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
No Connect.
CE1
CE4
CC
CC
CC
falls below V
falls below V
= 0V. The normal application of this signal is to control lithium powered current to
and
is lithium-backed and remains at a logic high when V
LI
CE2
. Connect
LI
. Read/write access is controlled by R/
. Connect
LI
LI
.
.
PE1
PE1
5 of 26
CCmin
CC
to battery-backed functions only.
PE2
is lithium-backed and remains at a logic high when V
= 0V. Because it is an I/O pin, it also forces a reset if pulled
level and the micro is in a reset state. When this occurs, the
to battery-backed functions only.
PE2
PE3
PE4
CE2
CE3
is lithium-backed and remains at a logic high when V
is not lithium-backed and can be connected to any type
is not lithium-backed and can be connected to any type
is lithium-backed and remains at a logic high when
is lithium-backed and remains at a logic high when
CC
CC
falls below V
< V
CC
CC
W
LI
. BD7–0 connect directly to an
< V
< V
and the micro has switched to
CC
LI
LI
.
.
LI
< V
CE1
.
LI
is lithium-backed. It
.
DS5001FP
CC
falls
CC
CE2
CE3
CC
)