ADUC814ARU-REEL Analog Devices, ADUC814ARU-REEL Datasheet - Page 24
ADUC814ARU-REEL
Manufacturer Part Number
ADUC814ARU-REEL
Description
MicroConverter/ Small Package 12-Bit ADC with Embedded Flash MCU
Manufacturer
Analog Devices
Datasheet
1.ADUC814ARU-REEL.pdf
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ADuC814
ADCCON3 (ADC CONTROL SFR 3)
The ADCCON3 register controls the operation of various calibration modes as well as giving an indication of ADC busy status.
SFR Address
SFR Power-On Default
Table 8. ADCCON3 SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
BUSY
Name
BUSY
GNCLD
AVGS1
AVGS0
OFCLD
MODCAL
TYPECAL
SCAL
GNCLD
Description
ADC Busy Status Bit.
BUSY is a read-only status bit that is set during a valid ADC conversion or calibration cycle.
Busy is automatically cleared by the core at the end of a conversion or calibration cycle.
Gain Calibration Disable Bit.
This bit enables/disables the gain calibration coefficients from affecting the ADC results.
Set to 0 to enable gain calibration coefficient
Set to 1 to disable gain calibration coefficient.
Number of Averages Selection Bits.
This bit selects the number of ADC readings averaged for each bit decision during a calibration cycle.
AVGS1
Offset Calibration Disable Bit.
This bit enables/disables the offset calibration coefficients from affecting the ADC results.
Set to 0 to enable offset calibration coefficient.
Set to 1 to disable the offset calibration coefficient
Calibration Mode Select Bit.
This bit should be set to 1 for all calibration cycles.
Calibration Type Select Bit.
This bit selects between offset (zero-scale) and gain (full-scale) calibration.
Set to 0 for offset calibration.
Set to 1 for gain calibration.
Start Calibration Cycle Bit.
When set, this bit starts the selected calibration cycle.
It is automatically cleared when the calibration cycle is completed.
0
0
1
1
F5H
00H
AVGS0
0
1
0
1
AVGS1
Number of Averages
15
1
31
63
AVGS0
Rev. A | Page 24 of 72
OFCLD
MODCAL
TYPECAL
SCAL
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