QT118H-S ETC, QT118H-S Datasheet - Page 8

• Manufacturer Part Number: QT118H-S
• Description: CHARGE-TRANSFER TOUCH SENSOR
• Manufacturer: ETC

Since the IC operates in a burst mode, almost all
the power is consumed during the course of each
burst. During the time between bursts the sensor
is quiescent.
For proper operation a 100nF (0.1uF) ceramic
bypass capacitor should be used between Vdd and
Vss; the bypass cap should be placed very close
to the device’s power pins. Without this capacitor
the part can break into high frequency oscillation,
get physically hot, and stop working.
3.4.1 M
Measuring average power consumption is a
challenging task due to the burst nature of the
device’s operation. Even a good quality RMS DMM
will have difficulty tracking the relatively slow burst
rate.
The simplest method for measuring average current is to
replace the power supply with a large value low-leakage
electrolytic capacitor, for example 2,700µF. 'Soak' the
capacitor by connecting it to a bench supply at the desired
operating voltage for 24 hours to form the electrolyte and
reduce leakage to a minimum. Connect the capacitor to the
circuit at T=0, making sure there will be no detections during
the measurement interval; at T=30 seconds measure the
capacitor's voltage with a DMM. Repeat the test without a
load to measure the capacitor's internal leakage, and
subtract the internal leakage result from the voltage droop
measured during the QT118H load test. Be sure the DMM is
connected only at the end of each test, to prevent the DMM's
impedance from contributing to the capacitor's discharge.
Supply drain can be calculated from the adjusted voltage
droop using the basic charge equation:
where C is the large supply cap value, t is the elapsed
measurement time in seconds, and
voltage droop on C.
A good approximation can be made to this method by using
a 2,700µF cap across the circuit, and inserting a 220 ohm
resistor in series with a current meter in the power wire.
3.4.2 ESD, RFI
ESD protection. In cases where the electrode is placed
behind a dielectric panel, the IC will be protected from direct
static discharge. However even with a panel transients can
still flow into the electrode via induction, or in extreme cases
via dielectric breakdown. Porous materials may allow a
spark to tunnel right through the material. Testing is required
to reveal any problems. The device does have diode
protection on its terminals which can absorb and protect the
device from most induced discharges, up to 20mA; the
usefulness of the internal clamping will depending on the
dielectric properties, panel thickness, and rise time of the
ESD transients.
ESD dissipation can be aided further with an added diode
protection network as shown in Figure 2-7, in extreme cases.
Because the charge and transfer times of the QT118H are
relatively long, the circuit can tolerate very large values of
Re1 and Re2, more than 100k ohms combined in most
cases where the electrode load is small. The added diodes
lq
EASURING
i
✁VC
t
S
P
UPPLY
ROTECTION
C
URRENT
V is the adjusted
shown
high-conductance diodes) will shunt the ESD transients
away from the part, and Re1 will current limit the rest into
the QT118H's own internal clamp diodes. C1 should be
around 10µF if it is to absorb positive transients from a
human body model standpoint without rising in value by
more than 1 volt. If desired C1 can be replaced with an
appropriate zener diode. Directly placing semiconductor
transient protection devices or MOV's on the sense lead is
not advised; these devices have extremely large amounts of
nonlinear parasitic C which will swamp the capacitance of
the electrode.
Re1 and Re2 should be as large as possible given the load
value of Cx, Cf, and the diode capacitances of D1 and D2.
Re1 and Re2 should be low enough to permit at least 6 RC
time-constants to occur during the charge and transfer
phases. Re1 should be about 20% of Re2. Cf is used for RFI
suppression; see below.
Re3 functions to isolate the transient from the Vdd pin;
values of around 1K ohms are reasonable.
As with all protection networks, it is crucial that transients be
led away from the circuit. PCB ground layout is crucial; the
ground connections to D1, D2, and C1 should all go back to
the power supply ground or preferably, if available, a chassis
ground connected to earth. The currents should not be
allowed to traverse the area directly under the IC.
If the electrode operates behind glass or insulating plastics
thicker than 2mm, D1 and D2 can be safely deleted.
However it is still wise to use Re1, of a value as large as can
be tolerated. Values up to 100K and sometimes well beyond
can usually be tolerated quite well.
If the device is connected to an external circuit via a cable or
long twisted pair, it is possible for ground-bounce to cause
damage to the Out pin; even though the transients are led
away from the IC itself, the connected signal or power
ground line will act as an inductor causing a high differential
voltage to build up on the Out wire with respect to ground. If
this is a possibility the Out pin should have a resistance Re4
in series with it to limit current; this resistor should be as
large as can be tolerated by the load.
RFI Suppression. PCB layout, grounding, and the structure
of the input circuitry have a great bearing on the success of
a design to withstand RF fields.
Figure 2-7 ESD Protection
(1N4150,
BAV99
or
equivalent
low-C
7