TP3410 National Semiconductor, TP3410 Datasheet

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... TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver General Description The TP3410 is a complete monolithic transceiver for ISDN Basic Access data transmission at either end of the U inter- face Fully compatible with ANSI specification T1 601 it is built on National’s advanced double-metal CMOS process and requires only a single ...

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... U Interface and is available in NT and LT modes The Received Superframe Synch clock output is accessible on pin 25 by writing X’1C04 and X’100C (or X’100E) during device initialization See TP3410 users manual AN-913 Part II Section 4 18 Transmit 2B1Q signal differential outputs ...

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Pin Descriptions (Continued) PIN DESCRIPTIONS SPECIFIC TO MICROWIRE MODE ONLY ( Pin Symbol Description Receive 2B1Q signal differential inputs from the line transformer For normal full- b duplex operation these pins should ...

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Pin Descriptions (Continued) Pin Symbol Description The digital input for multiplexed B D and control data clocked by BCLK at the rate of 1 data bit per 2 BCLK cycles and 32 data bits per 8 kHz ...

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... Functional Description 1 1 Power-On Initialization When power is first applied power-on reset circuitry initializ- es the TP3410 and puts it into the power-down state in which all the internal circuits including the Master oscillator are inactive and in a low power state except for the Line- ...

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Functional Description (Continued) Framing Quat Positions 1–9 Bit Positions 1–18 Superframe Basic Frame Sync Word 1 1 ISW ISW Framing Quat Positions 1–9 ...

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... Activation section ACTIVATION CONTROL OVERVIEW The TP3410 contains an automatic sequencer for the com- plete control of the start-up activation sequence specified in the ANSI standard Both the ‘‘cold-start’’ and the fast ‘ ...

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... DSI or GCI Slave mode in Register CR1 A Digital Phase-Locked Loop (DPLL 2) on the TP3410 allows the MCLK frequency to be plesiochronous (i e free-running) with respect to the net- work clocks (BCLK and the 8 kHz FSa input) With a toler- ...

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Functional Description (Continued) Format 2 Format 2 is the IDL in which the 2B transfer is assigned to the first 19 bits of the frame on the Bx and Br pins Channels are as- signed as follows B1 (8 bits) ...

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Functional Description (Continued) Transmit slots are numbered relative to FSa and receive slots relative to FSb Shown with examples of offset frames and Time-slot Assignments FIGURE 3-3 DSI Format 3 (Time-Slot Assignment) Slave Mode FSa defines B1 channel for Tx ...

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... FSa FSb and the start of the first time-slot can be selected Channel Time-slot Assignment Format 3 Only (Microwire Mode) In Format 3 only the TP3410 provides programmable time- slot assignment for selecting the Transmit and Receive B channel time-slots Following power-on the device is auto- matically in Non-delayed Data Mode if Delayed Data Mode ...

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... Interrupt Stack with the priority order listed in Table III To shift data to and from the TP3410 CCLK must be pulsed high 16 times while CS is low Data on the CI input is shifted into the serial input register on the rising edge of each CCLK ...

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... Functional Description (Continued) The TP3410 has an enhanced MICROWIRE port such that it can connect to standard MICROWIRE master devices (such an NSC’s HPC and COP families) as well as the SCP (serial control port) interface master from the Motorola micro-con- troller family SCP is supported on devices such as ...

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... Status Registers originate messages in the Moni- tor channel under control of the Interrupt Stack (in the same manner as when the TP3410 is used in Microwire Mode) In addition a protocol is used based on the E and A bits in byte 4 to provide an acknowledgement of each Monitor ...

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Functional Description (Continued) Byte 1 (Register Address) Function Operation (NOP Write OPR Readback OPR Write CR1 Readback CR1 Write CR2 0 ...

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Functional Description (Continued) Byte 1 (Register Address) Function READABLE CONFIGURATION REGISTERS Default (No Change Write Cycle) OPR Contents CR1 Contents CR2 Contents ...

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... Modes CMS 1 for DSI Master may be used in either Modes but when in LT Mode must also send X 1840 See the TP3410 User’s Manual AN-913 Section 4 5 for details In GCI Mode (MW e selects GCI Master or Slave BEX B Channel Exchange This command enables the two B channels to be ex- ...

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... H12 With SH9 1 a TP3410 Rev 3 3 device in state H11 will generate a DP interrupt when it receives the ‘‘dea 0’’ bit but is prevented from transitioning to device state ...

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Functional Description (Continued) RFS Remote Febe Select RFS 1 (default state) e The state of the outgoing bit is computed based on the state of the TFB (bit 1) in TXM56 register The TFB blt is set by the software ...

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Functional Description (Continued) Byte DR5 DR4 DR3 DR2 DR1 DR0 At Power-On Reset this register is initialized Receive D Channel Time-Slot Assignment Select DR5–DR0 SR1–SR0 DR5 –DR0 bits define the ...

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Functional Description (Continued Transmit M5 M6 Spare Bits Register TXM56 (Write Only) Byte LEC M51 M61 M52 At Power-On Reset and each time the device is Deactivat- ed (or ...

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... Activation Commands PUP This command powers up the device and starts the oscillator PUP DR When the TP3410 is in the power-down state this command powers up the device and starts the oscillator In LT mode only when the device is activated this code is a Deactivation Request which forces the device through the specified de- activation sequence by setting ‘ ...

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... Activation Status Indicators DP LSD When the TP3410 is deactivated either powered up or powered down the Line Signal Detector sets this indicator if it detects an incoming 10 kHz wake-up tone If the device is powered down the ...

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... TP3410 User’s Manual AN-913 BOARD LAYOUT While the pins of the TP3410 are well protected against electrical misuse it is recommended that the standard CMOS practice of applying GND to the device before any other connections are made should always be followed In ...

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Applications Information (Continued) Note matching may be required to meet the longitudinal balance specification depending on the Longitudinal impedance to ground of the line interface The 15 and 1k resistors in the line interface circuit should be ...

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... Transmit Pulse Amplitude Transmit Pulse Linearity Input Pulse Amplitude Note 1 GND refers to GNDA GNDD1 and GNDD2 commoned together V Note 2 In the circuits shown in Figures 9 and 10 terminated in 135 is described in the TP3410 Users Manual AN-913 Storage Temperature Range Current at Lo Current at Any Digital Output 7V ...

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Timing Characteristics Symbol Parameter FMCK Master Clock Frequency Master Clock Tolerance MCLK XTAL Input Clock Jitter tMH Clock Pulse Width tML Hi Low for MCLK tMR Rise and Fall Time tMF of MCLK DIGITAL INTERFACE ( Figures 11 12 and ...

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Timing Characteristics (Continued) Symbol Parameter MICROWIRE CONTROL INTERFACE (see Figure 14 ) tCH CCLK High Duration tCL CCLK Low Duration tSIC Setup Time CI Valid to CCLK High tHCI Hold Time CCLK High to CI Invalid tSSC Setup Time from ...

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Timing Diagrams FIGURE 11 Non-Delayed Data Timing Mode (Formats 1 and 3) FIGURE 12 Delayed Data Timing Mode (Formats 1 2 and 9151 – 28 (Shown with TS0 Selected 9151 – ...

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... Timing Diagrams (Continued) Note output (GCI Master high for 8 bit intervals (16 BCLK cycles input (GCI Slave FIGURE 14a TP3410 Enhanced MICROWIRE Control Port Timing FIGURE 13 GCI and Format 4 Timing 9151 – 23 must be high for 1 BCLK cycle ...

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... Timing Diagrams (Continued) FIGURE 14b TP3410 Normal MICROWIRE CLOCK Format FIGURE 14c TP3410 Alternate MICROWIRE CLOCK Format 9151 – 9151 – 30 ...

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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Ceramic Dual-In-Line Package (J) Order Number TP3410J NS Package Number J28A 2 A critical component is any component of a life ...