M66257 Mitsubishi, M66257 Datasheet
M66257
Available stocks
Related parts for M66257
M66257 Summary of contents
Page 1
... DESCRIPTION The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word figuration which uses high-performance silicon gate CMOS process technology. It allows simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over mul- tiple lines ...
Page 2
... MITSUBISHI DIGITAL ASSP M66257FP 8-BIT 2 LINE MEMORY (FIFO are written into 2-line delay data and Q ...
Page 3
... RRES, RCK GND GND, Output open 25ns WCK RCK f = 1MHz f = 1MHz MITSUBISHI DIGITAL ASSP M66257FP 5120 8-BIT 2 LINE MEMORY (FIFO) Ratings Unit –0.5 ~ +7.0 V –0 0 –0 0 660 mW –65 ~ 150 °C Unit Max. 5 ° ...
Page 4
... GND = 0V, unless otherwise noted Parameter = 5V ± 10%, GND = 0V, unless otherwise noted) CC Parameter – WRES “L” level period – RRES “L” level period MITSUBISHI DIGITAL ASSP M66257FP 5120 8-BIT 2 LINE MEMORY (FIFO) Limits Unit Min. Typ. Max ...
Page 5
... RCK RE t ODIS(HZ) 90 ODIS(LZ 10 =30pF : 10% of output amplitude and t is 90% of ODIS(HZ) MITSUBISHI DIGITAL ASSP M66257FP 5120 8-BIT 2 LINE MEMORY (FIFO =1k L SW1 Q n SW2 C =5pF : OEN ODIS R =1k L Parameter SW1 t ...
Page 6
... Disable cycle WCKL WEH NWES NWEH n+1) (n+2) Reset cycle Cycle RESS RESH (n) MITSUBISHI DIGITAL ASSP M66257FP 5120 8-BIT 2 LINE MEMORY (FIFO) Cycle n+3 Cycle n+4 t WES (n+3) (n+4) WRES = “H” Cycle 1 Cycle 2 t NRESS (0) (1) ( “L” ...
Page 7
... RCKL REH NRES NREH t ODIS HIGH-Z (n+1) (n+2) Reset cycle Cycle RESS RESH t AC (n) (0) ( MITSUBISHI DIGITAL ASSP M66257FP 5120 8-BIT 2 LINE MEMORY (FIFO) Cycle n+3 Cycle n+4 t RES OEN (n+3) (n+ RRES = “H” Cycle 1 Cycle 2 t NRESS (0) (1) ( “L” ...
Page 8
... To stop reading write data at n cycle, input WCK for up to the rising edge of n+1 cycle. When the cycle next to n cycle is a disable cycle, input of WCK for a cycle is required after a disable cycle as well. 8 MITSUBISHI DIGITAL ASSP M66257FP 5120 8-BIT 2 LINE MEMORY (FIFO) ...
Page 9
... D (n–1)<1>* (n)<1>* n Cycle n <0>* RCK Q (n–1)<0>* n Cycle n+1 Cycle n+2 (n) (n+1) (n+2) Cycle n–2 Cycle n–1 invalid Cycle 0 <2>* (0) <2>* Cycle 0 <1>* (0)<1>* (n)<0>* MITSUBISHI DIGITAL ASSP M66257FP 5120 8-BIT 2 LINE MEMORY (FIFO) of cycle n becomes invalid. n Cycle n+3 (n+3) Cycle n (n) Cycle n <2>* (n–1)<2>* (n)<2>* Cycle n <1>* (n–1)<1>* (n)<1>* <0>*, <1>* and <2>* indicates a line value. 9 ...
Page 10
... Q Q 2-line delay Primary scanning direction Line n image data Line (n–1) image data 10 17 Line (n–1) Line N+K { (N–A)+(N–B)} = N+K { 2N–(A+B)} Line (n+ Laplacean coefficient MITSUBISHI DIGITAL ASSP M66257FP 5120 8-BIT 2 LINE MEMORY (FIFO) Corrected image data K ...