MC92300CG Motorola, MC92300CG Datasheet - Page 3

• Manufacturer Part Number: MC92300CG
• Description: VITERBI Decoder for Digital TV
• Manufacturer: Motorola

MC92300
Rev.1.3
SYMCLK
BITCLK
VDCLK
VDCLK_DIV2 - VDCLK/2
RESET_N
VLCK
VFF
VEF
SR[2:0]
VO
VC0,VC1[2:0] - Soft Decision Input
SDA
DSA[6:0]
SCL
TESTSEL,
FREF,
TESTOUT,
VCOCTL
VDCLK_DIV2
- System Clock (output clock)
- Input Clock
- Asynchronous Reset
- Viterbi Decoder in Lock
- FIFO Full Flag
- FIFO Empty Flag
- Selected Rate
- Viterbi Decoder Output
- Data Bus of I
- Slave Address of I
- Clock Line of I
- APLL pins
- System Clock (input clock)
TESTOUT
TESTSEL
SYMCLK
VDCLK
VC1[2
VC1[0]
VC0[2]
VC1[1]
VC0[1]
VC0[0
OVDD
OVDD
OVDD
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
FREF
VDD
VDD
VDD
VSS
VSS
VSS
]
]
2
C-interface
2
V
S
S
C-interface
O
V
S
S
P
E
N
I
D
V
C
O
C
T
L
2
V
T
S
T
O
V
D
D
C-interface
V
T
S
T
I
[
1
]
O
V
D
D
V
T
S
T
I
[
0
]
S
D
A
R
E
S
E
T
_
N
S
C
L
R
E
S
E
T
_
A
S
Y
N
C
D
S
A
[
0
]
D
S
A
[
1
]
O
V
D
D
128QFP
O
V
S
S
V
D
D
V
S
S
V
S
S
V
D
D
O
V
S
S
O
V
D
D
D
S
A
[
2
]
D
S
A
[
3
]
D
S
A
[
4
]
D
S
A
[
5
]
D
S
A
[
6
]
O
V
D
D
O
V
S
S
V
D
D
V
S
S
V
S
S
V
D
D
O
V
S
S
O
V
D
D
VTSTI[1:0]
VTSTO
TEST_SE
MOTOROLA Device Test Pins:
51, 56-62, 105, 110-115, 120
(don’t connect these pins)
NOT CONNECTED Pins:
27, 33, 34, 88-94, 99-102
RESET_ASYNC
TEST_MODE
T
E
S
T
_
M
O
D
E
T
E
S
T
_
S
E
O
V
D
D
O
V
S
S
V
S
S
V
D
D
OVSS
OVDD
OVSS
OVDD
OVSS
OVDD
OVSS
OVDD
OVSS
SR[2]
SR[1]
SR[0]
OVDD
VSS
VDD
VSS
BITCLK
VLCK
OVSS
VO
VDD
VSS
VFF
VEF
VDD
- Test pins
- Test output
- Teset for Scan Test
- Test pin for Scan Mode
- Test pin for Scan Mode
MOTOROLA
3