GS71108AJ-10 ETC [List of Unclassifed Manufacturers], GS71108AJ-10 Datasheet - Page 5

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GS71108AJ-10

Manufacturer Part Number
GS71108AJ-10
Description
128K x 8 1Mb Asynchronous SRAM
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
AC Test Conditions
AC Characteristics
Read Cycle
* These parameters are sampled and are not 100% tested
Rev: 1.04a 10/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
1.
2.
3.
Output disable to output in High Z (OE)
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Chip enable to output in low Z (CE)
Output enable to output valid (OE)
Output hold from address change
Include scope and jig capacitance.
Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
Output load 2 for t
Chip enable access time (CE)
Output reference level
Input reference level
Address access time
Input high level
Input low level
Input rise time
Parameter
Input fall time
Read cycle time
Output load
Parameter
LZ
, t
HZ
, t
OLZ
and t
OHZ
Symbol
t
t
t
OHZ
t
OLZ
Conditions
t
t
t
t
t
HZ
LZ
RC
AA
AC
OE
OH
V
V
tr = 1 V/ns
tf = 1 V/ns
Fig. 1& 2
*
*
*
*
IH
IL
1.4 V
1.4 V
= 0.4 V
= 2.4 V
Min
7
3
3
0
5/14
-7
Max
3.5
7
7
3
3
Min
8
3
3
0
-8
Max
3.5
3.5
8
8
4
DQ
Min
10
3
3
0
DQ
-10
Output Load 1
Output Load 2
Max
© 2001, Giga Semiconductor, Inc.
10
10
4
5
4
5pF
GS71108ATP/J/SJ/U
VT = 1.4 V
1
3.3 V
Min
12
3
3
0
50
589
434
-12
Max
12
12
30pF
5
6
5
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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