HN58X24128FPIE RENESAS [Renesas Technology Corp], HN58X24128FPIE Datasheet - Page 8

• Manufacturer Part Number: HN58X24128FPIE
• Manufacturer: RENESAS [Renesas Technology Corp]

HN58X24128I/HN58X24256I
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to
distinguish each device and device address pins should be connected to V
code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one
device can be activated.
Pin Connections for A0 to A2
Memory size
128k bit
256k bit
Note:
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. When the WP is low, write operation for all memory arrays are allowed. The read
operation is always activated irrespective of the WP pin status. WP should be fixed high or low during
operations since WP does not provide a latch function.
Write Protect Area
WP pin
status
V
V
Rev.4.00, Dec.14.2004, page 8 of 20
IH
IL
1. “V
CC
Max connect
number
8
8
Write protect area
128k bit
Upper 1/8 (16k bit)
Normal read/write operation
/V
SS
” means that device address pin should be connected to V
Pin connection
A2
V
V
CC
CC
/V
/V
SS
SS
*
1
A1
V
V
CC
CC
/V
/V
SS
SS
A0
V
V
CC
CC
/V
/V
SS
SS
256k bit
Upper 1/8 (32k bit)
Note
CC
or V
CC
or V
SS
. When device address
SS
.