HT82K68E_07 HOLTEK [Holtek Semiconductor Inc], HT82K68E_07 Datasheet - Page 12

• Manufacturer Part Number: HT82K68E_07
• Description: Multimedia Keyboard Encoder 8-Bit OTP MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Note: u means unchanged
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem powers up or when it awakes from the HALT state.
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RESET pin, the SST delay is disabled.
Any wake-up from HALT will enable the SST delay.
The functional unit chip reset status is shown below.
Timer Counter
A timer counter (TMR) is implemented in the
HT82K68E. The timer counter contains an 8-bit pro-
grammable count-up counter and the clock may come
from the system clock divided by 4.
Using the internal instruction clock, there is only one ref-
erence time-base.
There are two registers related to the timer counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the start-
ing value be placed in the timer counter preload register
and reading TMR gets the contents of the timer counter.
The TMRC is a timer counter control register, which de-
fines some options.
In the timer mode, once the timer counter starts count-
ing, it will count from the current contents in the timer
Rev. 2.00
Program Counter
Prescaler
WDT
Timer counter
Input/output ports
Stack Pointer
TO
0
u
0
1
1
Bit No.
0~3
4
5
6
7
PDF
0
u
1
u
1
RESET reset during power-up
RESET reset during normal operation
RESET wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
Label
TON
TM0
TM1
000H
Clear
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of the stack
RESET Conditions
Unused bit, read as "0"
To enable/disable timer counting (0= disabled; 1= enabled)
Unused bit, read as "0"
10= Timer mode (internal clock)
TMRC (0EH) Register
12
counter to FFH. Once overflow occurs, the counter is
reloaded from the timer counter preload register and
generates the interrupt request flag (TF; bit 5 of INTC) at
the same time.
To enable the counting operation, the timer ON bit
(TON; bit 4 of TMRC) should be set to 1. In the case of
timer counter OFF condition, writing data to the timer
counter preload register will also reload that data to the
timer counter. But if the timer counter is turned on,
data written to it will only be kept in the timer counter
preload register. The timer counter will still operate until
overflow occurs. When the timer counter (reading TMR)
is read, the clock will be blocked to avoid errors. As
clock blocking may results in a counting error, this must
be taken into consideration by the programmer.
Function
Reset Configuration
Reset Timing Chart
Reset Circuit
HT82K68E
July 10, 2007