OX16C950 OXFORD [Oxford Semiconductor], OX16C950 Datasheet - Page 15

• Manufacturer Part Number: OX16C950
• Description: High Performance UART with 128 byte FIFOs
• Manufacturer: OXFORD [Oxford Semiconductor]

6
The three address lines select the various registers in the UART. Since there are more than 8 registers, selection of the registers
is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:
1. LCR[7]=1 enables the divider latch registers DLL and DLM.
2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables
3. ACR[7]=1 enables access to the 950 specific registers.
4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 17.
Data Sheet Revision 1.2
OXFORD SEMICONDUCTOR LTD.
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
Register
650 mode
750 mode
950 mode
9-bit data
9-bit data
650/950
550/750
550/750
650/950
Name
MCR
Normal
Normal
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
LSR
MSR
THR
RHR
IER
FCR
SPR
Mode
Mode
LCR
Mode
Mode
mode
mode
ISR
DLM
DLL
R
EGISTER
1,2
3,5
3
3,4
1
3
4
3
1
3
Address
000
000
001
010
010
011
100
101
110
111
000
001
D
ESCRIPTION
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
R
prescale
interrupt
access
T
Divisor
Bit 7
mask
Baud
latch
Data
Error
DCD
CTS
ABLES
RHR Trigger
RHR Trigger
Table 4: Standard 550 Compatible Registers
enabled
Unused
Unused
FIFOs
Level
Level
Tx Empty
interrupt
Bit 6
mask
break
mode
RTS
IrDA
Tx
RI
Unused
XON-Any
Alternate
Special
Control
Divisor latch bits [15:8] (Most significant byte)
Detect
CTS &
Divisor latch bits [7:0] (Least significant byte)
Empty
Bit 5
Char.
mode
Force
parity
sleep
FIFO
(Enhanced mode)
Flow
THR
DSR
Size
RTS
Interrupt priority
Indexed control register offset value bits
THR Trigger
Temporary data storage register and
Level
Data to be transmitted
Unused
Internal
Unused
Enable
Bit 4
Break
Sleep
mode
Odd /
parity
even
Loop
Back
CTS
Rx
Data received
interrupt
Framing
Modem
(Int En)
Trigger
Enable
Mode /
enable
OUT2
Bit 3
Parity
mask
DMA
Error
Delta
DCD
Tx
Interrupt priority
(All modes)
interrupt
Number
RI edge
Rx Stat
data bit
Trailing
of stop
OUT1
Bit 2
Parity
9
mask
Flush
Error
THR
bits
th
Rx
OX16C950 rev B
interrupt
Overrun
THRE
Bit 1
Flush
mask
Delta
RHR
Error
RTS
DSR
Data length
interrupt
Interrupt
pending
RxRDY
RxRDY
Enable
data bit
Bit 0
mask
Delta
FIFO
9
DTR
Page 15
CTS
th
Tx