ADUM5200ARWZ2 AD [Analog Devices], ADUM5200ARWZ2 Datasheet - Page 8

• Manufacturer Part Number: ADUM5200ARWZ2
• Description: Dual-Channel Isolators with Integrated DC/DC Converter
• Manufacturer: AD [Analog Devices]

ADuM5200/5201/5202
Parameter
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
1
2
3
4
5
6
7
8
9
10
11
12
13
All voltages are relative to their respective ground.
The contributions of supply current values for all four channels are combined at identical data rates.
V
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the V
The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of its internal power consumption.
I
additional dynamic supply current. It reflects the minimum current operating condition.
I
dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load.
This current is available for driving external loads at the V
representing the maximum dynamic load conditions. Refer to Power Consumption section for calculation of available current at less than maximum data rate.
I
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
measured from the 50% level of the rising edge of the V
load within the recommended operating conditions.
DD1(Q)
DD1(D)
DD1(MAX)
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
t
t
Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
ISO
Channel-to-Channel Matching,
Channel-to-Channel Matching,
at Logic High Output
at Logic Low Output
Refresh Rate
PHL
PSK
supply current available for external use when all data rates are below 2Mbps. At data rates above 2Mbps data I/O channels will draw additional current
is the magnitude of the worst-case difference in t
propagation delay is measured from the 50% level of the falling edge of the V
Codirectional Channels
Opposing-Directional Channels
Pulse-Width Distortion, |t
Propagation Delay Skew
is the minimum operating current drawn at the V
is the typical input supply current with all channels simultaneously driven at maximum data rate of 25Mbps with full capacitive load representing the maximum
is the input current under full dynamic and V
Change vs. Temperature
17
16
PLH
− t
PHL
17
|
11
ISO
PHL
DD1
load conditions.
Ix
and/or t
Symbol
PWD
t
t
t
t
|CM
|CM
f
ISO
signal to the 50% level of the rising edge of the V
PSK
PSKCD
PSKCD
R
r
pin when there is no external load at V
/t
pin. All channels are simultaneously driven at maximum data rate of 25Mbps with full capacitive load
F
H
L
|
|
PLH
that is measured between units at the same operating temperature, supply voltages, and output
Rev. PrA| Page 8 of 23
Min
25
25
Ix
signal to the 50% level of the falling edge of the V
Typ
5
2.5
35
35
1.0
ISO
and the I/O pins are operating below 2Mbps, requiring no
Max
6
45
6
15
Ox
signal.
Unit
ns
ps/°C
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
Preliminary Technical Data
ISO
power budget.
Test Conditions
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
L
L
L
L
L
L
Ix
Ix
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= V
= 0 V, V = 1000 V,
DD
Ox
or V
signal. t
ISO
, V
PLH
CM
propagation delay is
= 1000 V,