RT9166A RICHTEK [Richtek Technology Corporation], RT9166A Datasheet - Page 10

• Manufacturer Part Number: RT9166A
• Description: 300/600mA, Ultra-Fast Transient Response LDO Regulator
• Manufacturer: RICHTEK [Richtek Technology Corporation]

RT9166/A
For recommended operating conditions specification of
RT9166/A, where T
temperature of the die (125°C) and T
ambient temperature. The junction to ambient thermal
resistance θ
packages, the thermal resistance θ
standard JEDEC 51-3 single-layer thermal test board. The
maximum power dissipation at T
by following formula :
P
SOT-23-3 packages
P
SOT-89 packages
P
SOT-223 packages
P
TO-252 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
resistance θ
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power allowed.
www.richtek.com
10
D (MAX)
D (MAX)
D (MAX)
D (MAX)
Figure 1. Derating Curves for RT9166/A Packages
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
= ( 125°C − 25°C) / 250°C/W = 0.400W for
= ( 125°C − 25°C) / 175°C/W = 0.571W for
= ( 125°C − 25°C) / 135°C/W = 0.740W for
= ( 125°C − 25°C) / 68°C/W = 1.470W for
0
TO-252
SOT-223
SOT-89
SOT-23-3
JA
JA
. For RT9166/A packages, Figure 1 of
is
25
Ambient Temperature (°C)
layout dependent. For SOT-23-3
J(MAX)
50
is the maximum junction
A
= 25°C can be calculated
JA
75
J(MAX)
is 250°C/W on the
A
Single Layer PCB
is the operated
and thermal
100
125
PCB Layout
Good board layout practices must be used or instability
can be induced because of ground loops and voltage drops.
The input and output capacitors MUST be directly
connected to the input, output, and ground pins of the
device using traces which have no other currents flowing
through them.
The best way to do this is to layout C
device with short traces to the V
The regulator ground pin should be connected to the
external circuit ground so that the regulator and its
capacitors have a “single point ground”.
It should be noted that stability problems have been seen
in applications where “vias” to an internal ground plane
were used at the ground points of the device and the input
and output capacitors. This was caused by varying ground
potentials at these nodes resulting from current flowing
through the ground plane. Using a single point ground
technique for the regulator and it’ s capacitors fixed the
problem. Since high current flows through the traces going
into V
leads to these pins so there is no voltage drop in series
with the input and output capacitors.
Optimum performance can only be achieved when the
device is mounted on a PC board according to the diagram
below :
IN
GND
and coming from V
V
IN
Figure 2. SOT-23-3 Board Layout
OUT
, Kelvin connect the capacitor
IN
DS9166/A-19 April 2008
, V
OUT
IN
and C
, and ground pins.
V
OUT
OUT
near the