RT9719 RICHTEK [Richtek Technology Corporation], RT9719 Datasheet - Page 8

• Manufacturer Part Number: RT9719
• Description: Charging System Safety Device
• Manufacturer: RICHTEK [Richtek Technology Corporation]

RT9719
junction to ambient. The maximum power dissipation can
be calculated by following formula :
P
Where T
temperature, T
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT9719, where T
ambient temperature. The junction to ambient thermal
resistance θ
SOT-23-6 package is 250°C/W on the standard JEDEC
51-3 single-layer thermal test board. The maximum power
dissipation at T
formula :
P
WDFN-8L 2x2 packages
P
SOT-23-6 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
resistance θ
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
www.richtek.com
8
D(MAX)
D(MAX)
D(MAX)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Figure 3. Derating Curves for RT9719 Packages
= ( T
0
= (125°C − 25°C) / (165°C/W) = 0.606 W for
= (125°C − 25°C) / (250°C/W) = 0.400 W for
WDFN-8L 2x2
SOT-23-6
J(MAX)
JA
J(MAX)
JA
for WDFN-8L 2x2 package is 165°C/W and
A
. For RT9719 packages, the Figure 3 of
A
25
is the ambient temperature and the θ
is the maximum operation junction
= 25°C can be calculated by following
− T
J(MAX)
Ambient Temperature (°C)
A
) / θ
is 125°C and T
50
JA
75
J(MAX)
Four Layouts PCB
A
is the operated
100
and thermal
125
JA
is
From Adapter
From Adapter
Input capacitor must be
placed between GND
and ACIN to reduce
noise.
Layout Consideration
The RT9719 is a protection device. Careful PCB layout is
necessary. For best performance, place all peripheral
components as close to the IC as possible. A short
connection is highly recommended. The following
guidelines should be strictly followed when designing a
PCB layout for the RT9719.
GND
GND
Input capacitor must be
placed between GND
and ACIN to reduce
noise.
The exposed pad, GND must be soldered to a large
ground plane for heat sinking and noise prevention. The
through-hole vias located at the exposed pad is
connected to ground plane of internal layer.
ACIN traces should be wide to minimize inductance and
handle the high currents. The trace running from input
to chip should be placed carefully and shielded strictly.
The capacitors must be placed close to the part. The
connection between pins and capacitor pads should be
copper traces without any through-hole via connection.
C
IN
C
ACIN
GND
IN
ACIN
ACIN
ACIN
GND
NC
Figure 4. PCB Layout Guide
1
2
3
4
2
3
9
6
5
4
The exposed pad,
GND must be soldered
to a large ground
plane for heat sinking
and noise prevention.
The exposed pad,
GND must be soldered
to a large ground plane
for heat sinking and
noise prevention.
8
7
6
5
GATEDRV
CHRIN
ISENSE
ISENSE
ISENSE
CHRIN
GATEDRV
To Baseband
Gate Controller
To Baseband
Gate Controller
To Baseband Charger Controller
DS9719-01 April 2011
To Battery
To Battery
The capacitor must be
placed between GND
and ACIN to reduce
noise.
To Baseband
Charger Controller
The capacitor
must be placed
between GND
and ACIN to
reduce noise.