D2-45057_10 INTERSIL [Intersil Corporation], D2-45057_10 Datasheet - Page 8

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D2-45057_10

Manufacturer Part Number
D2-45057_10
Description
Intelligent Digital Amplifier PWM Controller and Audio Processor
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
SPI™ Master Mode Interface Port Timing
±10%. All grounds at 0.0V. All voltages referenced to ground.
SPI™ Slave Mode Interface Port Timing
±10%. All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
SYMBOL
SCK(CPHA = 1, CPOL = 0)
SCK(CPHA = 0, CPOL = 0)
t
t
t
t
t
t
t
t
WI
WI
H
H
V
S
V
S
MISO(CPHA = 0)
MOSI Valid From Clock Edge
MISO Setup to Clock Edge
MISO Hold From Clock Edge
nSS Minimum Width
MISO Valid From Clock Edge
MOSI Setup to Clock Edge
MOSI Hold From Clock Edge
nSS Minimum Width
MOSI
nSS
8
DESCRIPTION
DESCRIPTION
D2-45057, D2-45157
t
FIGURE 3. SPI TIMING
V
T
A
T
A
= +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
= +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
t
t
V
S
t
H
MIN
MIN
10
10
-
3 system clocks + 2ns
3 system clocks + 2ns
3 system clocks + 2ns
1 system clock + 2ns
1 system clock + 2ns
t
MAX
MAX
WI
8
-
-
July 29, 2010
UNIT
UNIT
ns
ns
ns
FN6785.0

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