PFS704 POWERINT [Power Integrations, Inc.], PFS704 Datasheet - Page 4

• Manufacturer Part Number: PFS704
• Description: High Power PFC Controller with Integrated High-Voltage MOSFET
• Manufacturer: POWERINT [Power Integrations, Inc.]

Pin Functional Description
VOLTAGE MONITOR (V) Pin:
The V pin is tied to the rectified AC rail through an external
resistor. Internal circuitry detects the peak of the input line
voltage which resembles a full-wave rectified waveform. The
rectified high-voltage bus is connected directly to the V pin
voltage through a large resistor (4 MW for PFS70x and PFS71x;
9 MW for PFS72x) to minimize power dissipation and standby
power consumption. A small ceramic capacitor (0.1 mF for
PFS70x and PFS71x; 0.047 mF for PFS72x) is required from the
VOLTAGE MONITOR pin to SIGNAL GROUND pin to bypass
any switching noise present on the rectified bus. This pin also
features both brown-in and brown-out protection.
FEEDBACK (FB) Pin:
The FEEDBACK pin is high input-impedance reference terminal
that connects to a feedback resistor network. This pin will also
feature fast overvoltage and undervoltage detection circuitry
that will disengage the internal power MOSFET in the event of a
system fault. A 10 nF capacitor is required between the
FEEDBACK to SIGNAL GROUND pins; this capacitor must be
placed very close to the device on the PCB to bypass any
switching noise. This pin is also used for loop compensation.
BIAS POWER (VCC) Pin:
This is a 10-12 VDC bias supply used to power the IC. The bias
voltage must be externally clamped to prevent the VCC pin
from exceeding 13.4 VDC.
Rev. D 12/11
Figure 3.
4
VOLTAGE MONITOR (V)
FEEDBACK (FB)
V
operating frequency as a function of output power for increased efficiency
(PFS704-716).
(V
OFF
LINE INTERFACE
M
OFF
Detector
ON
Peak
is a function of the error-voltage (V
= 0.8 V for PFS723-729).
I
INPUT
VPK
PFS704-729EG
Functional Block Diagram.
(I
Input UV
UV-
/I
UV+
Reference
FB
Internal
)
V
OV
FB
FB
REF
UV
OFF
/
+
+
-
-
Transconductance
+
-
Comparator
Error-Amplifier
6 V
Fast OV
UV Comparator
E
Input Voltage
7 kHz
) and is used to reduce the average
Filter
Emulation
M
sense scale factor which
voltage derived from I
is function of peak line
ON
1 kHz
Filter
is the switch current
I
VPK
+
-
SIGNAL GROUND (G)
“Off-time derived with
constant Volt-Sec
V
O
M
-V
ON
IN
Frequency
VIN
I
S
Slide
V
C
E
INT
V
V
OFF
E
C
The internal derived error-voltage (V
INT
+
Comparator
+
-
-
Comparator
regulates the output voltage
INTERNAL
Figure 2.
SIGNAL GROUND (G) Pin:
Discrete components used in the feedback circuit, including
loop compensation, decoupling capacitors for the supply (VCC)
and line-sense (V) must be referenced to the G pin. The
SIGNAL GROUND pin must not be tied to the SOURCE pin.
SOURCE (S) Pin:
This pin is the source connection of the power switch.
DRAIN (D) Pin:
This is the tab and drain connection of the internal power switch.
SUPPLY
SUPERVISOR
TIMER
Exposed Metal (On Edge)
Internally Connected
to GROUND Pin
Pin Configuration.
Latch
1 2 3 4 5
BIAS POWER (VCC)
+
-
FB
E
OTP
)
OV/UV
Input UV
E Package (eSIP-7G)
V
CC+
7
7
Driver
OCP
5 4 3 2 1
V
CC
LEB
START
SOFT
OTP
Sense
FET
www.powerint.com
+
-
I
S
Exposed Metal
(On Edge)
Internally
Connected to
DRAIN Pin
Exposed Pad
(Backside)
Internally
Connected to
DRAIN Pin
(see eSIP-7G
Package
Drawing)
I
OCP
SOURCE (S)
DRAIN (D)
PI-5333-113010
PI-5334-083110
MOSFET
Power