SI9119 VISHAY [Vishay Siliconix], SI9119 Datasheet - Page 7

• Manufacturer Part Number: SI9119
• Description: Programmable Duty Cycle Controller
• Manufacturer: VISHAY [Vishay Siliconix]

Start-Up
Si9118/Si9119 are designed with internal depletion mode
MOSFET capable of powering directly from the high input bus
voltage. This feature eliminates the typical external start-up
circuit saving valuable space and cost. But, most of all, this
feature improves the converter efficiency during full load and
has an even greater impact on light load. With an input bus
voltage applied to the +V
9.3 V. The UVLO circuit prevents the controller output driver
section from turning on, until V
order to maximize converter efficiency, the designer should
provide an external bootstrap winding to override the internal
V
internal depletion mode MOSFET regulator is disabled and
power is derived from the external V
provides power to the internal circuity as well as providing
supply voltage to the gate drive circuit.
Soft-Start/Enable
The soft-start time is externally programmable with capacitor
connected to the SS/EN pin. A constant current source
provides the current to the SS/EN pin to generate a linear
start-up time versus the capacitance value. The SS/EN pin
clamps the error amplifier output voltage, limiting the rate of
increase in duty cycle. By controlling the rate of rise in duty
cycle gradually, the output voltage rises gradually preventing
the output voltage from overshooting. The SS/EN pin can also
be used to enable or disable the output driver section with an
external logic signal.
Synchronization
The synchronization to external clock is easily accomplished
by connecting the external clock into the SYNC pin (Si9119
only). The logic high to low transition synchronizes the clock.
The external clock frequency must be at least 5% faster than
the internal clock frequency.
Reference Voltage
The reference voltage for the Si9118/Si9119 are set at 4.0 V.
The reference voltage is not connected to the non-inverting
inputs of the error amplifier, therefore, the minimum output
voltage is not limited to reference voltage. The V
requires a 0.1- F decoupling capacitor.
Error Amplifier
The error amplifier gain-bandwidth product is critical parameter
which determines the transient response of converter.
transient response is function of both small and large signal
responses. The small signal response is determined by the
feedback compensation network while the large signal response
is determined by the inductor di/dt slew rate.
Document Number: 70815
S-60752—Rev. B, 05 Apr-99
CC
regulator. If external V
IN
CC
pin, the V
voltage is greater than 9.3 V, the
CC
voltage exceeds 8.7 V. In
CC
CC
supply. The V
voltage is regulated to
Besides the
CC
REF
supply
New Product
The
pin
inductance value, the error amplifier gain-bandwidth determines
the converter response time. In order to minimize the response
time, Si9118/Si9119 is designed with a 2.7-MHz error amplifier
gain-bandwidth product to provide the widest converter
bandwidth possible.
PWM Mode
The converter operates in PWM mode if the PWM/PSM pin is
connected to V
line voltage vary, the Si9118/Si9119 maintain constant
switching frequency until they reach minimum duty cycle.
Once the output voltage regulation is exceeded with minimum
duty cycle, the switching frequency will continue to decrease
until regulation is achieved.
controlled by the external R
typical oscillator frequency curve. In PWM mode, output ripple
noise is constant reducing EMI concerns as well as simplifying
the filter to minimize the system noise.
Pulse Skipping Mode
If the PWM/PSM pin is connected to –V
converter can operate in either PWM or PSM mode depending
on the load current. The converter automatically transitions
from PWM to PSM or vise versa to maintain output voltage
regulation. In PSM mode, the MOSFET switch is turned on
until the peak current sensed voltage reaches 100 mV and the
output voltage meets or exceeds its regulation voltage. The
converter is operating in pulse skipping mode because each
pulse delivers excess energy into the output capacitor forcing
the output voltage to exceed its regulation voltage. By forcing
the output voltage to exceed the regulation voltage,
succeeding pulses are skipped until the output voltage drops
below the regulation point. Therefore, switching frequency will
continue to reduce during PSM control as the demand for
output current decreases. The pulse skipping mode cuts down
the switching losses, the dominant power consumed during
low output current, thereby maintaining high efficiency
throughout the entire load range. With PWM/PSM pin in logic
low state, the converter transitions back into PWM mode, if the
peak current sensed voltage of 100 mV does not generate the
required output voltage. In the region between pulse skipping
mode and PWM mode, the controller may transition between
the two modes, delivering spurts of pulses. This may cause
the current waveform to look irregular, but this will not overly
affect the ripple voltage.
efficiency remains high.
Programmable Duty Cycle Control
The maximum duty cycle limit is controlled by the voltage on
D
while 0.0 V generates 0% duty cycle. The 80% duty cycle is
maximum default condition at 1-MHz switching frequency. The
D
from the reference voltage.
MAX
MAX
pin. A D
voltage can be easily generated using resistor divider
MAX
REF
voltage of 3.2 V generates 80% duty cycle
pin or logic high. As the load current and
Even in this transitional mode,
osc
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The switching frequency is
and C
Vishay Siliconix
Si9118/Si9119
osc
IN
pin (logic low), the
as shown by the
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