VP216 MITEL [Mitel Networks Corporation], VP216 Datasheet - Page 5

• Manufacturer Part Number: VP216
• Description: Dual 90MHz 6-Bit Analog to Digital Converter with VCO
• Manufacturer: MITEL [Mitel Networks Corporation]

Device Description
Fig.2). Included on chip is a high bandwidth ADC driver
amplifier, a 6-bit analog to digital converter, latches and TTL
data outputs. The VP216 also has the necessary bias
voltages for the reference resistor chain in the ‘flash’
architecture of the ADC and has an optional VCO or external
oscillator interface.
Analog Input
non-inverting ADC driver amplifiers, which provide the
necessary bandwidth, gain, offset and low impedance
required to drive the ADC. The amplifier has been designed
so that an input of 0 volts will produce an output level equal
to the voltage present at the middle of the ADC resistor
chain, (VRM = 3V typ.). This is achieved by an internal
feedback loop within each amplifier which compares the
amplifier output with VRM, (see Fig.3). This voltage will
produce a transition binary code of 011111 to 100000 at the
output of the ADC.
Reference Voltage
with two op-amps provides all the necessary bias voltages
for the ADC reference resistor chain, (VRB), (VRM) and
(VRT). VRB, VRM and VRT have been brought out to pins 8,
7 and 6 respectively and should be decoupled with 100nF
capacitors close to the package pins.
Digital Interface
have been optimized to interface with devices in close
proximity to the VP216 and are designed to provide
satisfactory logic levels at speeds up to 90MHz into a fanout
of one and a total load capacitance of 10pF. All data outputs
should have approximately equivalent loading to ensure
proper setup and hold timing. For capacitive loads in excess
of 10pF, output buffers are recommended.
SIGNAL
INPUT
The VP216 is a dual 90MHz 6-bit ADC system, (see
The analog inputs, (AIN_I,Q) are A.C. coupled into the
An on chip band gap voltage reference circuit combined
The TTL data output pins, (DI0-DI5) and (DQ0-DQ5)
COMP_(Q,I)
C
Fig.3 DC offset internal feedback loop.
C
EXT.
C
COMP
EXT.
ADC DRIVER
AMP
DC SHIFT
VRM
TO ADC
Clock Interface
in a number of ways. With the CLKSEL pin tied low the on
chip VCO is selected. With the CLKSEL pin tied high the
external TTL clock input is selected.
conversion and output stages of the device as shown in the
timing diagram (see Fig.4). The output of the ADC driver amp
is sampled when the comparator array is latched after a
rising edge of the input clock. Latched data is then presented
to the TTL data outputs and latched on the falling edge of the
input clock. The clock interface also provides a TTL clock
output on pin 27. This output is limited to driving capacitive
loads of 10pF. Output buffers are recommended for loads in
excess of 10pF.
The VP216 clock interface allows the ADC to be clocked
The clock signal to the ADC synchronizes the sampling,
Code
00
01
31
32
33
62
63
CLKSEL
1
0
Table 3: Output coding
1 Volt Full Scale
Least +Ve Valid
Most +Ve Valid
16mV = 1LSB
Input Voltage
Table 2
Input
Input
External Clock
Clock Source
VCO
000000
000001
011111
100000
100001
111110
111111
Binary
VP216
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