XC61F_2 TOREX [Torex Semiconductor], XC61F_2 Datasheet - Page 5

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XC61F_2

Manufacturer Part Number
XC61F_2
Description
Voltage Detectors, Delay Circuit Built-In
Manufacturer
TOREX [Torex Semiconductor]
Datasheet

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■OPERATIONAL EXPLANATION
●CMOS output
●Timing Chart
② When V
③ When VI
④ When V
① When a voltage higher than the release voltage (V
⑤ Although V
⑥ Following transient delay time, V
Notes:
1. The difference between V
2. Release delay time (
Note that high impedance exists at V
V
applies to N-channel open drain configurations.
gradually fall. When a voltage higher than the detect voltage (V
input at V
be equal to the pull up voltage.
the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up voltage.
V
drain configuration and that voltage will be dependent on pull up.
DR
SS
level.
until V
IN
IN
N
IN
falls to a level below that of the minimum operating voltage (V
rises above the V
falls below V
IN
IN
.
will rise to a level higher than V
reaches the V
t
DLY
) represents the time it takes for V
DF
DR
, V
DR
and V
SS
OUT
level.
level (excepting levels lower than minimum operating voltage), V
IN
will be equal to the ground voltage (V
DF
will be output at V
OUT
represents the hysteresis range.
with the N-channel open drain configuration. If the pin is pulled up, V
DR
, V
OUT
DR
OUT
maintains ground voltage level via the delay circuit.
) is applied to the voltage input pin (VI
IN
. Note that high impedance exists with the N-channel open
to appear at V
DF
(t
) is applied to VIN, output (V
DLY
)
MIN
OUT
SS
) level (detect state). Note that this also
) output will become unstable. Because
once the said voltage has exceeded the
OUT
) will be equal to the
OUT
N
), the voltage will
will be equal to
OUT
XC61F
Series
will
5/14

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