ISPPAC-POWR1014A LATTICE [Lattice Semiconductor], ISPPAC-POWR1014A Datasheet - Page 17

• Manufacturer Part Number: ISPPAC-POWR1014A
• Description: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 3. Comparator Hysteresis vs. Trip-Point
The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed”
with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function without using any of
the PLD’s resources. Through the use of the multiplexer, voltage monitor’s ‘A’ output may be set to report either the
status of the ‘A’ comparator, or the window function of both comparator outputs. The voltage monitor’s ‘A’ output
indicates whether the input signal is between or outside the two comparator thresholds. Important: This windowing
function is only valid in cases where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’
comparator. Table 4 shows the operation of window function logic.
Table 4. Voltage Monitor Windowing Logic
Note that when the ‘A’ output of the voltage monitor circuit is set to windowing mode, the ‘B’ output continues to
monitor the output of the ‘B’ comparator. This can be useful in that the ‘B’ output can be used to augment the win-
dowing function by determining if the input is above or below the windowing range.
The third section in the ispPAC-POWR1014/A’s input voltage monitor is a digital filter. When enabled, the compara-
tor output will be delayed by a filter time constant of 64 µs, and is especially useful for reducing the possibility of
false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the
comparator output will be delayed by 16µs. In both cases, enabled or disabled, the filters also provide synchroniza-
tion of the input signals to the PLD clock. This synchronous sampling feature effectively eliminates the possibility of
race conditions from occurring in any subsequent logic that is implemented in the ispPAC-POWR1014/A’s internal
PLD logic.
The comparator status can be read from the I
face, please refer to the I
V
Trip-point B < V
Trip-point B < Trip-point A < V
IN
< Trip-point B < Trip-point A
Input Voltage
IN
< Trip-point A
2
C/SMBUS Interface section of this data sheet.
IN
Low Limit
Comp A
0.672
0.800
0.952
1.133
1.346
1.603
1.908
2.267
2.691
3.199
4.105
4.889
Trip-point Range (V)
0
0
1
2
75 mV
C interface (ispPAC-POWR1014A only). For details on the I
High Limit
0.806
0.960
1.143
1.360
1.612
1.923
2.290
2.719
3.223
3.839
4.926
5.867
Comp B
17
0
1
1
Hysteresis (mV)
0 (Disabled)
(B and Not A)
ispPAC-POWR1014/A Data Sheet
10
12
14
17
20
24
28
34
40
51
61
8
Window
0
1
0
Outside window, low
Inside window
Outside window, high
Comment
2
C inter-