ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 28

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
One can also program a user-defined skew between two outputs using the skew control units. Because the pro-
grammable skew is derived from the VCO frequency, as described in the previous section, the absolute skew is
very accurate. The typical error for any non-zero skew setting is given by the t
one is in fine skew mode with a VCO frequency of 500MHz, and selects a skew of 8TU, the realized skew will be
2ns, which will typically be accurate to within +/-30 ps. An example of error vs. skew setting can be found in the
chart ‘Typical Skew Error vs. Setting’ in the typical performance characteristics section. Note that this parameter
adds to output-to-output skew error only if the two outputs have different skew settings. The Bank1A and Bank3A
outputs in Figure 24 show how the various sources of skew error stack up in this case. Note that if two or more out-
puts are programmed to the same skew setting, then the contribution of the t
When outputs are configured or loaded differently, this also has an effect on skew matching. If an output is set to
support a different logic type, this can be accounted for by using the t
‘Switching Characteristics’. That table specifies the additional skew added to an output using LVPECL as a base-
line. For instance, if one output is specified as LVTTL (t
(t
shown in Figure 25a.
Figure 25. Output Timing Adders for Logic Type (a) and Output Slew Rate (b)
Similarly, when one changes the slew rate of an output, the output slew rate adders (t
the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are
measured. For example, in the case of outputs configured to the same logic type (e.g. LVCMOS 1.8V), if one output
is set to the fastest slew rate (1, t
660ps of skew between the two outputs, as shown in Figure 25b.
Other Features
Profile Select
The ispClock5500 stores all internal configuration data in on-board E
figuration profiles may be stored in each device. The choice of which configuration profile is to be active is specified
thought the profile select inputs PS0 and PS1, as shown in Table 7.
Table 7. Profile Select Function
Each profile controls the following internal configuration items:
IOO
• M divider setting
• N divider setting
• V divider settings
= 0ns), then one could expect 0.1ns of additional skew between the two outputs. This timing relationship is
LVPECL Output
(T
LVTTL Output
(T
IOS
IOS
= 0.1ns)
= 0)
(a)
IOS
0.1ns
= 0ps), and another set to slew rate 3 (t
PS1
0
0
1
1
PS0
28
IOO
0
1
0
1
LVCMOS Output
LVCMOS Output
(Slew rate=1)
(Slew rate=3)
= 0.1ns), and another output is specified as LVPECL
Active Profile
2
CMOS memory. Up to four independent con-
Profile 0
Profile 1
Profile 2
Profile 3
ispClock5500 Family Data Sheet
IOO
SKERR
output adders specified in the Table
IOS
SKERR
= 660ps), then one could expect
skew error term does not apply.
specification. For example, if
(b)
660ps
IOS
) can be used to predict