SP813MEP SIPEX [Sipex Corporation], SP813MEP Datasheet - Page 10
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SP813MEP
Manufacturer Part Number
SP813MEP
Description
Low Power Microprocessor Supervisory Circuits
Manufacturer
SIPEX [Sipex Corporation]
Datasheet
1.SP813MEP.pdf
(18 pages)
Figure 14. SP705/706/813L/813M Watchdog Timing Waveforms
Typically, WDO will be connected to the
non-maskable interrupt input (NMI) of a P.
When V
WDO will go LOW whether or not the watch-
dog timer has timed out. Normally this would
trigger an NMI but RESET goes LOW simulta-
neously, and thus overrides the NMI.
Figure 15. SP705/706 Timing Diagrams with WDI Tri-stated. The SP707/708/813L/813M RESET Output is the Inverse
of the RESET Waveform Shown.
OCT 17-06 RevB
CC
drops below the reset threshold,
RESET
RESET*
RESET*
WDO
WDO
WDI
MR*
V
CC
t
+5V
+5V
WP
+5V
+5V
+5V
+5V
+5V
+5V
0V
0V
0V
0V
0V
0V
0V
0V
SP705 Low Power Microprocessor Supervisory Circuits
* externally triggered LOW by MR,
*externally driven LOW
RESET is for the SP813L/813M only
V
RT
t
WD
10
If WDI is left unconnected, WDO can be used as
a low-line output. Since floating WDI disables
the internal timer, WDO goes LOW only when
V
tioning as a low-line output.
CC
t
falls below the reset threshold, thus func-
RS
V
RT
t
WD
t
RS
t
RS
t
MD
t
MR
t
WD
© 2006 Sipex Corporation