XR20M1170IL16 EXAR [Exar Corporation], XR20M1170IL16 Datasheet - Page 33

• Manufacturer Part Number: XR20M1170IL16
• Description: I2C/SPI UART WITH 64-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

REV. 1.0.0
MCR[2]: OP1# / TCR and TLR Enable
OP1# is not available as an output pin on the M1170. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the MSR and TCR registers at address offset 0x6 and the SPR and TLR
registers at address offset 0x7.
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output.
•
•
MCR[4]: Internal Loopback Enable
•
•
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
•
•
MCR[6]: IR Mode Enable (requires EFR bit-4=1 to write to this bit)
This bit enables the infrared mode and/or controls the infrared mode after power-up. See
Infrared Mode” on page 21
•
•
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the M1170 is programmed to use the Xon/Xoff flow control.
Logic 0 = Reserved (default).
Logic 1 = Enable IR Mode.
EFR[4]
EFR[4] MCR[2] Register at Address Offset 0x6
for complete details.
0
1
1
0
1
1
Table 12
T
T
ABLE
ABLE
MCR[2] Register at Address Offset 0x7
X
X
0
1
0
1
12: R
13: R
and
Modem Status Register (MSR)
Modem Status Register (MSR)
Trigger Control Register (TCR)
Scratchpad Register (SPR)
Scratchpad Register (SPR)
Trigger Level Register (TLR)
EGISTER AT
EGISTER AT
Table 13
33
below shows how these registers are accessed.
A
A
DDRESS
DDRESS
O
O
Figure
FFSET
FFSET
I2C/SPI UART WITH 64-BYTE FIFO
0
0
19.
X
X
6
7
XR20M1170
“Section 2.15,