XR68C192 EXAR [Exar Corporation], XR68C192 Datasheet - Page 15

• Manufacturer Part Number: XR68C192
• Description: DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
• Manufacturer: EXAR [Exar Corporation]

PROGRAMMING AND REGISTER DESCRIPTIONS
load value loaded and start counter command issued)
before programming the timer output to appear on OP3.
Use caution if the contents of a register are changed
during receiver/ transmitter operation as certain
changes can produce undesired results. For example,
changing the number of bits per character while the
transmitter is active can transmit an incorrect charac-
ter. The contents of the clock-select register (CSR) and
ACR Bit-7 should only be changed after the receiver(s)
and transmitter(s) have been issued software RX and TX
reset commands. Most bits of the mode registers
should not be changed during receiver/transmitter op-
eration, except that in Multidrop parity mode, the
address/data parity type bit can be changed at any
time.
44
Similarly, certain changes to the auxiliary control regis-
ter (ACR Bits 4-6) should only be made while the
counter/timer (C/T) is not used. Channel A mode regis-
ters MR1A and MR2A are accessed via an auxiliary
pointer. The pointer is set to mode register one (MR1A)
by RESET or by issuing a “reset pointer” command via
the channel A command register. Any read or write of
the mode register switches the pointer to mode register
two (MR2A). All subsequent accesses will address
MR2A unless the pointer is reset to MR1A as described
above. The channel B mode registers MR1B and MR2B
A3 A2 A1 A0
Rev. P1.10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
READ
Mode Register A (MR1A, MR2A)
Status Register A (SRA)
Reserved
Receiver Buffer A (RBA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Counter/Timer MSB (CUR)
Counter/Timer LSB(CLR)
Mode Register B (MR1B, MR2B)
Status Register B (SRB)
Reserved
Receiver Buffer B (RBB)
Interrupt-Vector Register (IVR)
Input Port (IP)
Start-Counter Command
Stop-Counter Command
15
are accessed by an identical pointer independent of the
channel A pointer. Mode, command, clock-select, and
status registers are duplicated for each channel to allow
independent operation and control (except that both
channels are restricted to baud rates that are in the
same set).
Output Port Configuration Register (OPCR)
WRITE
Mode Register A (MR1A, MR2A)
Clock-Select Register A (CSRA)
Command Register A (CRA)
Transmitter Buffer A (TBA)
Auxiliary Control Register (ACR)
Interrupt Mask Register (IMR)
Counter/ Timer Upper Register (CTUR)
Mode Register B (MR1B, MR2B)
Clock-Select Register B (CSRB)
Command Register B (CRB)
Transmitter Buffer B (TBB)
Interrupt-Vector Register (IVR)
Set Output Port Register (OPR) bits
Reset Output Port Register (OPR) bits
Counter/ Timer Lower Register (CTLR)
XR68C92/192