XR16C2850IJ EXAR [Exar Corporation], XR16C2850IJ Datasheet
XR16C2850IJ
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XR16C2850IJ Summary of contents
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NOVEMBER 2005 GENERAL DESCRIPTION 1 The XR16C2850 (2850 enhanced dual universal asynchronous receiver and transmitter (UART). Enhanced features include 128 bytes of TX and RX FIFOs, programmable TX and RX FIFO trigger level, FIFO level counters, automatic ...
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... XR16C2850 TXRDYB# 6 48-pin TQFP TXA 7 TXB 8 OP2B# 9 CSA# 10 CSB ORDERING INFORMATION ART UMBER ACKAGE XR16C2850CJ 44-Lead PLCC XR16C2850CM 48-Lead TQFP XR16C2850IJ 44-Lead PLCC XR16C2850IM 48-Lead TQFP 36 RESET 35 DTRB# 34 DTRA# 33 RTSA# OP2A RXRDYA# 30 INTA 29 INTB CLKSEL ...
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REV. 2.1.3 PIN DESCRIPTIONS 44-PLCC 48-TQFP N AME DATA BUS INTERFACE ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 44-PLCC 48-TQFP N AME RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 13 7 RXA 11 5 RTSA CTSA DTRA# ...
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REV. 2.1.3 44-PLCC 48-TQFP N AME RXB 10 4 RTSB CTSB DTRB DSRB CDB RIB OP2B ANCILLARY SIGNALS XTAL1 ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 44-PLCC 48-TQFP N AME CLKSEL - 25 CLK8/ RESET 39 36 VCC 44 42 GND 22 17 N.C. none 12 Pin type: I=Input, ...
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REV. 2.1.3 1.0 PRODUCT DESCRIPTION The XR16C2850 (2850) integrates the functions of 2 enhanced 16C550 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The configuration registers set is ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 2850 ...
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REV. 2.1.3 CSA 2.5 Channel A and B Internal Registers Each UART channel in the 2850 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 2.7 INTA and INTB Ouputs The INTA and INTB interrupt output output changes according to the operating mode and enahnced features setup. Table 3 and 4 summarize the operating behavior for ...
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REV. 2.1.3 Typical oscillator connections are shown in application note DAN108 on EXAR’s web site. 2.9 Programmable Baud Rate Generator A single Baud Rate Generator (BRG) is provided for the transmitter and receiver, allowing independent TX/RX channel control. The ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with CLK8/16 pin = 1 divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate ...
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REV. 2.1 IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock Transmit Shift Register (TSR) 2.10.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to 128 bytes ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 2.11 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 128 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X clock ...
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REV. 2.1 IGURE ECEIVER PERATION IN 16X or 8X Clock Receive Data Shift Register (RSR) 128 bytes by 11-bit wide FIFO Receive Data Byte and Errors N : Table-B selected as Trigger Table for OTE ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 2.14 Auto CTS Flow Control Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is monitored to suspend/restart the local transmitter. The ...
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REV. 2.1.3 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 2850 will halt transmission (TX) as soon ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 2.18 Infrared Mode The 2850 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends ...
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REV. 2.1.3 2.19 Sleep Mode with Auto Wake-Up The 2850 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 2.20 Internal Loopback The 2850 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular ...
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REV. 2.1.3 3.0 UART INTERNAL REGISTERS Each of the UART channel in the 2850 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete register ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS T 8: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR ...
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REV. 2.1 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DREV RD Bit DVID TRG ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16C2850 in the FIFO polled mode of ...
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REV. 2.1.3 IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the CTS# interrupt (default). • Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS T ABLE P ISR R RIORITY EGISTER EVEL ISR[0]: Interrupt Status • Logic ...
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REV. 2.1.3 FCR[3]: DMA Mode Select Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details. • Logic 0 = Normal Operation (default). • Logic 1 = DMA Mode. FCR[5:4]: Transmit FIFO Trigger Select ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and ...
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REV. 2.1.3 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS MCR[3]: OP2# Output / INT Output Enable This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used as a general ...
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REV. 2.1.3 LSR[3]: Receive Data Framing Error Tag • Logic framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS MSR[4]: CTS Input Status CTS# pin may function as automatic hardware flow control signal input enabled and selected by Auto CTS (EFR bit-7). Auto CTS flow control allows ...
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REV. 2.1.3 EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[7:6]: Reserved 4.12 FIFO Level Register (FLVL) - Read-Only The FIFO Level Register ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 4.16 Trigger Level / FIFO Data Count Register (TRG) - Write-Only User Programmable Transmit/Receive Trigger Level Register. TRG[7:0]: Trigger Level Register These bits are used to program desired trigger levels when ...
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REV. 2.1.3 FCTR[7]: Programmable Trigger Register Select • Logic 0 = Registers TRG and FC selected for RX. • Logic 1 = Registers TRG and FC selected for TX. 4.19 Enhanced Feature Register (EFR) Enhanced features are enabled or ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data ...
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REV. 2.1.3 T 16: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FLVL EFR XON1 XON2 XOFF1 XOFF2 FC I/O SIGNALS TX OP2# RTS# ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) Thermal Resistance (44-PLCC) ELECTRICAL CHARACTERISTICS DC ELECTRICAL ...
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REV. 2.1 14. XR16C2850 VOL S IGURE INK 0.00 0.10 0.20 0.30 F 15. XR16C2850 VOH S IGURE OURCE ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS AC ELECTRICAL CHARACTERISTICS TA (-40 + WHERE APPLICABLE S P YMBOL ARAMETER CLK Clock Pulse Duration OSC Oscillator Frequency OSC External Clock ...
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REV. 2.1.3 AC ELECTRICAL CHARACTERISTICS TA (-40 + WHERE APPLICABLE S P YMBOL ARAMETER TRST Reset Pulse Width N Baud Rate Divisor Bclk Baud Clock F 16 IGURE ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS F 18 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ATA US ...
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REV. 2.1 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS F 22 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# ...
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REV. 2.1 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX S D0:D7 (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO TXRDY IOW# ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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REV. 2.1.3 PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL 2.97V ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS PACKAGE DIMENSIONS (40 PIN PDIP Seating Plane L B Note: The control dimension is the millimeter column SYMBOL ...
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REV. 2.1.3 REVISION HISTORY Date Revision February 2000 Rev 1.0.0 Initial datasheet. April 2002 Rev 2.0.0 Changed to standard style format. Internal Registers are described in the order they are listed in the Internal Register Table. Clarified timing diagrams. ...
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XR16C2850 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS GENERAL DESCRIPTION .................................................................................................1 A ................................................................................................................................................1 PPLICATIONS F .....................................................................................................................................................1 EATURES F 1. XR16C2850 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT .................................................................................................................................2 ORDERING INFORMATION ...
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REV. 2.1.3 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 25 4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 25 4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... ...