AK5392-VS AKM [Asahi Kasei Microsystems], AK5392-VS Datasheet - Page 11

• Manufacturer Part Number: AK5392-VS
• Description: Enhanced Dual Bit 24Bit ADC
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
The external clocks which are required to operate the AK5392 are MCLK, LRCK(fs),SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. MCLK can be either 256fs or 384fs by setting CMODE pin.
When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Table 1 illustrates standard
audio word rates and corresponding frequencies used in the AK5392.
As the AK5392 includes the phase detect circuit for LRCK, the AK5392 is reset automatically when the
synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
AK5392 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 2 ). The
data format is MSB-first, 2's complement.
0188-E-01
System Clock Input
Serial Data Interface
Figure 1
Figure 2
Figure 3
Figure 4
Figure
32.0kHz
44.1kHz
48.0kHz
fs
SMODE2
H
H
L
L
11.2896MHz
12.2880MHz
8.1920MHz
Table 1 . Examples of System Clock
256fs
OPERATION OVERVIEW
Table 2 . Serial I/F Format
SMODE1
MCLK
H
H
L
L
12.2880MHz
16.9344MHz
18.4320MHz
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384fs
Slave Mode
Master Mode
I2S Slave Mode
I2S Master Mode
Mode
SCLK(128fs)
4.0960MHz
5.6448MHz
6.1440MHz
Lch=H, Rch=L
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
LRCK
[AK5392]
1997/11