AK4480 AKM [Asahi Kasei Microsystems], AK4480 Datasheet - Page 34

• Manufacturer Part Number: AK4480
• Description: High Performance 114dB 32-Bit DAC
• Manufacturer: AKM [Asahi Kasei Microsystems]

Addr Register Name
00H Control 1
■
Notes:
■
RSTN: Internal Timing Reset
DIF2-0: Audio Data Interface Modes
ECS: Ex DF I/F mode clock setting
EXDF: External Digital Filter I/F Mode (PCM only)
ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only)
MS1146-E-03
Data must not be written into addresses from 06H to 1FH.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default
values.
When the state of the PSN pin is changed, the AK4480 should be reset by the PDN pin.
Register Map
Register Definitions
Addr
00H
01H
02H
03H
04H
05H
0: Reset. All registers are not initialized.
1: Normal Operation (default)
0: BCK 32fs setting. MCLK, BCK are 512fs, 256fs and 128fs (default)
1: No BCK 32fs setting. MCLK, BCK are 768fs, 384fs and 192fs.
0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode
0: Disable: Manual Setting Mode (default)
1: Enable: Auto Setting Mode
Register Name
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
Control 4
Default
When ACKS bit is “1”, sampling frequency and MCLK frequency is detected automatically.
When internal clocks are changed, the AK4480 should be reset by the PDN pin or RSTN bit.
Initial value is “010” (Mode 2: 24-bit MSB justified).
ACKS
DZFE
ATT7
ATT7
INVL
D7
DP
(Table
ACKS
(Table
D7
0
DZFM
EXDF
ATT6
ATT6
INVR
15)
D6
0
14)
EXDF
D6
0
DCKS
ATT5
ATT5
ECS
SD
D5
0
- 34 -
ECS
D5
0
DCKB
ATT4
ATT4
DFS1
D4
0
0
D4
0
0
MONO
DFS0
ATT3
ATT3
DIF2
D3
0
DIF2
D3
0
DEM1
DZFB
ATT2
ATT2
DIF1
D2
0
DIF1
D2
1
SELLR
DEM0
ATT1
ATT1
DIF0
D1
0
DIF0
D1
0
SMUTE
SLOW
RSTN
ATT0
ATT0
[AK4480]
D0
0
2012/01
RSTN
D0
1